User`s guide

B
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14 Conver
g
ence and “Time Step Too Small Errors”
The parallel resistor gives a good model for eddy current loss
and limits the bandwidth of the inductor. The size of resistor
should be set to be equal to the inductor's impedance at the
frequency at which its Q begins to roll off.
Example: A common one millihenry iron core inductor begins
to roll off at no less than 100KHz. A good resistor value to use
in parallel is then R = 2*π*100e3*.001 = 628 ohms. Below the
roll-off frequency the inductor dominates; above it the resistor
does. This keeps the width of spikes from becoming
unreasonably narrow.
Bipolar Transistors Substrate
Junction
The UC Berkeley SPICE contains an unfortunate convention for
the substrate node of bipolar transistors. The collector-substrate
p-n junction has no DC component. If the capacitance model
parameters are specified (e.g., CJS) then the junction has
(voltage-dependent) capacitance but no DC current. This can
lead to a sneaky problem: if the junction is inadvertently
forward-biased it can create a very large capacitance. The
capacitance goes as a power of the junction voltage. Normal
junctions cannot sustain much forward voltage because a large
current flows. The collector-substrate junction is an exception
because it has no DC current.
If this happens it usually shows up at the first time step. It can
be spotted turning on the detailed operating point information
(.TRAN/OP) and looking at the calculated value of CJS for
bipolar transistors. The whole problem can be prevented by
using the PSpice model parameter ISS. This parameter “turns
on” DC current for the substrate junction.