User`s guide

Methodolo
g
y 16
-13
amount of overlap is less than the inertial delay of the device, the
prediction of a glitch is also suppressed by the simulator (see
Figure 16-15).
In this case, the factoring out of the 15 nsec common ambiguity
still results in a 5 nsec overlap of conflicting states. The glitch
is suppressed, however, because 5 nsec is less than TPLHMX-
TPLHMN (the computed inertial delay value of the AND gate,
6 nsec).
Note
Glitch suppression can be overridden by settin
g
the pulse-width rejection threshold parameter
(TPWRT) in the device’s I/O Model.
Methodolo
gy
The combination of component tolerances and the functional
response of a circuit design to a specific stimulus presents a
major challenge to the designer: to be certain that all copies of
the circuit that are built operate properly. Well-designed
systems have a high degree of immunity from the effects of
varying combinations of individual component tolerances.
The usefulness of digital worst-case timing simulation as an aid
to identifying design problems is dependent upon the nature of
the stimulus applied to the design. It is the simulation of signal
propagation through the network that enables you to observe the
timing relationships among various devices, and make
adjustments to the design as necessary.
25 75
55 90
TPLHMN=40
TPLHMX=60
TPLHMN=10
TPLHMX=45
15 30
TPLHMN=4
TPLHMX=10
Fi
g
ure 16-15
Glitch Suppression Example 3
This is not intended to be a
comprehensive discussion of the
application of di
g
ital worst-case
timin
g
simulation in the desi
g
n
process. Rather, it is a
su
gg
ested startin
g
point for
understandin
g
the results of your
simulation.