User`s guide

Reconver
g
ence Hazard 16
-11
In the event that discounting the common ambiguity does not
preclude the X being latched (or, in the case of simple gates, a
glitch being predicted), the situation is called a reconvergence
hazard. This is nothing more than a convergence hazard with the
conflicting signal ambiguities having a common origin.
To get the greatest benefit from digital worst-case simulation,
consider the areas of the circuit where signal timing is most
critical and make use of constraint checkers (see the online
MicroSim PSpice A/D Reference Manual for more information
about digital primitives) where appropriate. These devices
identify specific timing violations, taking into account the actual
signal ambiguities (resulting from the elements’ MIN/MAX
delay characteristics). The most common areas of concern are
often:
• data/clock signal relationships
• clock pulse-widths
• bus arbitration timing
Signal ambiguities that converge (or reconverge) on wired nets
or buses having multiple drivers may also produce hazards in a
manner similar to the behavior of logic gates. In such cases, the
simulator will factor out any common ambiguity that may exist
before reporting the existence of a hazard condition.
The use of constraint checkers to validate signal behavior and
interaction in these areas of your design allows timing problems
to be identified at the earliest possible time. Otherwise, a timing-
related failure is only identifiable by realizing that the circuit is
not producing the desired (expected) results at some point
during the simulation.
Of course, it could be very difficult to pinpoint the cause of the
problem. See Methodology
on page 16-13 for discussion of
digital worst-case timing simulation methodology.