User`s guide

6 Di

ital Worst-Case Timin

Analysis

Identification of Timin

Hazards

Timing hazard is the term applied to situations in which the

response of a device cannot be properly predicted due to

uncertainty in the arrival times of signals applied to its inputs.

Consider the following signal transitions (0-1, 1-0) being

applied to the AND gate.

ure 16-5

Timing Hazard Example

It is clear that the state of the output does not (and should not)

change, since at no time do both input states qualify the gate, and

the arrival times of the transitions are known.

Conver

ence Hazard

Consider the situation where there are ambiguities associated

with the signal transitions 0-R-1 and 1-F-0, which have a certain

amount of overlap; it is no longer certain which of the transitions

happens first. The output could pulse (0-1-0) at some point

because the input states may qualify the gate. On the other hand,

the output could remain stable at the 0-state. This is called a

convergence hazard, so named because the reason for the glitch

occurrence is the convergence of the conflicting ambiguities at

two primitive inputs.

Gate primitives (including LOGICEXP primitives) which are

presented with simultaneous opposing R and F levels may

produce a pulse of the form 0-R-0, or 1-F-1.

For example, a two-input AND gate with the inputs shown

below, produces the output shown.

ure 16-6

Convergence Hazard Example