User`s guide

16
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4 Di
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ital Worst-Case Timin
g
Analysis
the duration of the timing ambiguity result that represents a
primitive’s output change.
For example, consider the model of a BUF device in the
following figure.
U5 BUF $G_DPWR $G_DGND IN1 OUT1 ; BUFFER model
+ T_BUF IO_STD
.MODEL T_BUF UGATE ( ; BUF timing model
+ TPLHMN=15ns TPLHTY=25ns TPLHMX=40ns
+ TPHLMN=12ns TPHLTY=20ns TPHLMX=35ns)
Fi
g
ure 16-1
Timing Ambiguity Example 1
The application of the instantaneous 0-1 transition at 5 nsec in
this example produces a corresponding output result. Given the
delay specifications in the timing model, the output edge occurs
at a MIN of 15 nsec later and a MAX of 40 nsec later. The region
of ambiguity for the output response is from 20 to 45 nsec (from
TPLHMN and TPLHMX values). Similar calculations apply to
a 1-0 transition at the input, using TPHLMN and TPHLMX
values.
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