User`s guide

16
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2 Di
g
ital Worst-Case Timin
g
Analysis
Di
g
ital Worst-Case
Timin
g
Manufacturers of electronic components generally specify
component parameters (such as propagation delays in the case
of logic devices) as having tolerances. These are expressed as
either an operating range, or as a spread around a typical
operating point. The designer then has some indication of how
much deviation from typical one might expect for any of these
particular component delay values.
.
Realizing that any two (or more) instances of a particular type of
component may have propagation delay values anywhere within
the published range, designers are faced with the problem of
ensuring that their products are fully functional when they are
built with combinations of components having delay
specifications that fall (perhaps randomly) anywhere within this
range.
Historically, this has been done by making simulation runs using
minimum (MIN), typical (TYP), and maximum (MAX) delays,
and verifying that the product design is functional at these
extremes. But, while this is useful to some extent, it does not
uncover circuit design problems that occur only with certain
combinations of slow and fast parts. True worst-case
simulation, as provided by PSpice A/D, does just that.
Other tools called timing verifiers are sometimes used in the
design process to identify problems that are indigenous to circuit
definition. They yield analyses that are inherently pattern-
independent and often pessimistic in that they tend to find more
problems than will truly exist. In fact, they do not consider the
actual usage of the circuit under an applied stimulus.
PSpice A/D does not provide this type of static timing
verification. Worst-case timing simulation, as provided by
PSpice A/D, is a pattern-dependent mechanism that allows a
designer to locate timing problems subject to the constraints of
a specific applied stimulus.
Compared to Analo
g
Worst-Case
Analysis
Di
g
ital worst-case timin
g
simulation is
different from analo
g
worst-case
analysis in several ways. Analo
g
worst-case analysis is implemented
as a sensitivity analysis for each
parameter which has a tolerance,
followed by a projected worst-case
simulation with each parameter set to
its minimum or maximum value. This
type of analysis is
g
eneral since any
type of variation caused by any type of
parameter tolerance can be studied.
But it is time consumin
g
since a
separate simulation is required for
each parameter. This does not always
produce true worst-case results, since
the al
g
orithm assumes that the
sensitivity is monotonic over the
tolerance ran
g
e.
The techniques used for di
g
ital worst-
case timin
g
simulation are not
compatible with analo
g
worst-case
analysis. It is therefore not possible to
do combined analo
g
/di
g
ital worst-
case analysis and simulation and
g
et
the correct results. PSpice A/D allows
di
g
ital worst-case simulation of mixed-
si
g
nal and all-di
g
ital circuits; any
analo
g
sections are simulated with
nominal values.
Systems containin
g
embedded
analo
g
-within-di
g
ital sections do not
g
ive accurate worst-case results; they
may be optimistic or pessimistic. This
is because analo
g
simulation can not
model a si
g
nal that will chan
g
e
volta
g
e at an unknown point within
some time interval.
not
included
in: