User`s guide

Analyzin

Results 14

-29

unrelated origins, therefore nothing in common) at the inputs to

gate G1, PSpice A/D reports the occurrence as an AMBIGUITY

CONVERGENCE hazard. This means that the output of G1

may glitch.

Note that the output fans out to two devices, G2 and L1. The

effects of a glitch on G1 in this case do not reach the circuit

output P1, because that path is not sensitized (the other input to

G2 being held LO blocks the symptom). But, because G1’s

output is also used to clock latch L1, the effects of a glitch could

result in visibly incorrect behavior on output P2. This is an

example of a persistent hazard.

A persistent hazard is a timing violation or hazard that has a

potential effect on a primary (external) circuit output or on the

internal state (stored state or memory elements) of the design.

For the design to be considered reliable, such timing hazards

must be corrected.

PSpice A/D fully distinguishes between state uncertainty and

time uncertainty. When a hazard occurs, PSpice A/D propagates

...

e1 e2

FF1 FF2

ure 14-2

Circuit with a Timing Error

ure 14-3

Circuit with Timing Ambiguity Hazard