User`s guide

Internal Time Steps in Transient Analyses 11
-17
Internal Time Steps in
Transient Anal
y
ses
During analog analysis, PSpice A/D maintains an internal time
step which is continuously adjusted to maintain accuracy while
not performing unnecessary steps. During periods of inactivity,
the internal time step is increased. During active regions, it is
decreased. The maximum internal step size can be controlled by
specifying so in the Step Ceiling text box in the Transient dialog.
PSpice A/D will never exceed either the step ceiling value or
two percent of the total transient run time, whichever is less.
The internal time steps used may not correspond to the time
steps at which information has been requested to be reported.
The values at the print time steps are obtained by 2
nd
-order
polynomial interpolation from values at the internal steps.
When simulating mixed analog/digital circuits, there are
actually two time steps: one analog and one digital. This is
necessary for efficiency. Since the analog and digital circuitry
usually have very different time constants, any attempt to lock
them together would greatly slow down the simulation. The time
step shown on the PSpice A/D display during a transient
analysis is that of the analog section.
See Chapter 14,Digital
Simulation, for more information
on the di
g
ital timin
g
analysis of
PSpice A/D.