User`s guide

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38 Di
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ital Device Modelin
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B, C, D) have a setup/hold time of 20 ns in reference to the CLK
signal. We are also checking that ENP and ENT have a setup/
hold time of 20 ns with respect to the 0 to 1 transition of the
CLK signal, but only when the conditions in the WHEN
statement are met. All of the delay and constraint checking
values were taken directly from the actual data sheet. This
makes the delay modeling both easy and accurate.
All of the above primitives and modeling methods, as well as a
few special cases that are not covered here, can be found in the
Digital Devices chapter of the online MicroSim PSpice A/D
Reference Manual.
* 74160 Synchronous 4-bit Decade Counters with
asynchronous clear
* Modeled using LOGICEXP, PINDLY, & CONSTRAINT devices
.SUBCKT 74160 CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I
C_I D_I
+ QA_O QB_O QC_O QD_O RCO_O
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
*
U160LOG LOGICEXP(14,20) DPWR DGND
+ CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I
+ QDBAR QA QB QC QD
+ CLK ENP ENT CLRBAR LOADBAR A B C D
+ CLKBAR RCO JA JB JC JD KA KB KC KD EN
+ D0_GATE IO_STD IO_LEVEL={IO_LEVEL}
+ LOGIC:
+ CLK = { CLK_I } ;Buffering
+ ENP = { ENP_I }
+ ENT = { ENT_I }
+ CLRBAR = { CLRBAR_I }
+ LOADBAR = { LOADBAR_I }
+ A = { A_I }
+ B = { B_I }
+ C = { C_I }
+ D = { D_I }
+ CLKBAR = { ~CLK } ;Logic expressions
+ LOAD = { ~LOADBAR }
+ EN = { ENP & ENT }
+ I1A = { LOAD | EN }
+ I2A = { ~(LOAD & A) }
+ JA = { I1A & ~(LOAD & I2A) }
+ KA = { I1A & I2A }
+ I1B = { (QA & EN & QDBAR) | LOAD }
+ I2B = { ~(LOAD & B) }
+ JB = { I1B & ~(LOAD & I2B) }
+ KB = { I1B & I2B }