User`s guide

Creatin
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a Di
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ital Model Usin
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the PINDLY and LOGICEXP Primitives 7
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signal can go inactive before the active clock edge. Again, the
_LH and _HL forms are available. The difference between
RELEASETIME and SETUPTIME checking is that
simultaneous CLOCK/DATA transitions are never allowed
(this assumes a nonzero hold time). RELEASETIME is usually
not used in conjunction with SETUPTIME or HOLDTIME.
Width
WIDTH does the minimum pulse-width checking. MIN_HI/
MIN_LO is the minimum time that the node can remain HI/
LOW. The value must be a nonnegative constant, or expression.
A value of 0 means that any pulse width is allowed. At least one
of MIN_HI or MIN_LO must be used within a WIDTH section.
Freq
FREQ checks the frequency. MINFREQ/MAXFREQ is the
minimum/maximum frequency that is allowed on the node in
question. The value must be a nonnegative floating point
constant or expression measured in hertz. At least one of
MINFREQ or MAXFREQ must be used within a FREQ section.
AFFECTS clauses (not used in this example) can be included in
constraints to describe how the simulator should associate the
failure of a constraint check with the outputs (paths through the
device) of the PINDLY. This information does not affect the
logic state of the outputs but provides causality detail used by
the error tracking mechanism in Probe.
The 74160 Example
In the 74160 example, we are checking that the maximum clock
frequency (CLK) is not more than 25 MHz and the pulse width
is 25 ns. We are also checking that the CLRBAR signal has a
minimum LO pulse width of 20 ns, and that the 4 data inputs (A,