User`s guide

Creatin
g
a Di
g
ital Model Usin
g
the PINDLY and LOGICEXP Primitives 7
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Pin-to-Pin Dela
y
(PINDLY
Primitive)
The delay and constraint specifications for the model are
specified using the PINDLY primitive. The PINDLY primitive
is evaluated every time any of its inputs or outputs change. See
the Digital Devices chapter in the online MicroSim PSpice A/D
Reference Manual for more information.
For the 74160, we have five delay paths, the four flip-flop
outputs to subcircuit outputs QA...QD to QA_O...QD_O, and
RCO to RCO_O. The five paths are seen in the Delay &
Constraint section of the schematic. For delay paths, the number
of inputs must equal the number of outputs. Since the 74160
does not have TRI-STATE outputs, there are no enable signals
for this example, but there are ten reference nodes. The first four
(CLK, LOADBAR, ENT, and CLRBAR) are used for both the
pin-to-pin delay specification and the constraint checking. The
last six (ENP, A, B, C, D, and EN) are used only for the
constraint checking.
The PINDLY primitive also allows constraint checking of the
model. It can verify the setup, hold times, pulse width, and
frequency. It also has a general mechanism to allow for user-
defined conditions to be reported. The constraint checking only
reports timing violations; it does not affect the propagation
delay or the logic state of the device. Since the timing
parameters are generally specified at the pin level of the actual
device, the checking is normally done at the interface pins of the
subcircuit after the appropriate buffering has been done.
BOOLEAN
The keyword BOOLEAN begins the boolean assignments
which define temporary variables that can be used later in the
PINDLY primitive. The form is:
boolean variable = {boolean expression}
The curly braces are required.