User`s guide

Creatin
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a Di
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ital Model Usin
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the PINDLY and LOGICEXP Primitives 7
-31
name, interface pin list, and parameter list is the LOGICEXP
primitive. It contains everything in the component that can be
expressed in terms of simple combinational logic. The logic
expression device also serves to buffer other input signals that
will go to the PINDLY primitive. In this case, LOGICEXP
buffers the ENP_I, ENT_I, CLK_I, CLRBAR_I, LOADBAR_I,
and four data signals. See the Digital Devices chapter in the
online MicroSim PSpice A/D Reference Manual for more
information.
For our 74160 example, the logic expression (LOGICEXP) has
fourteen inputs and twenty outputs. The inputs are the nine
interface input pins in the subcircuit plus five feedback signals
that come from the flip-flops (QA, QB, QC, QD, and QDBAR).
The flip-flops are primitive devices themselves and are not part
of the logic expression. The outputs are the eight J-K data inputs
to the flip-flops, RCO, the four data lines used internal to the
logic expression (A, B, C, D), and the seven control lines: CLK,
CLKBAR, EN, ENT, ENP, CLRBAR, and LOADBAR.
The schematic representation of the device shows buffers on
every input signal of the model, while the logic diagram of the
device in the data book shows buffers or inverters on only the
CLRBAR_I, CLK_I, and LOADBAR_I signals. We have added
buffers to the inputs to minimize the insertion of A-to-D
interfaces when the device is driven by analog circuitry. The
best example is the CLK signal. With the buffer in place, if the
CLK signal is analog, one A-to-D interface device will be
inserted into the circuit by the simulator. If the buffer was not
present, then an interface device would be inserted at the CLK
pin of each of the flip-flops. The buffers have no delay
associated with them, but by minimizing the number of A-to-D
interfaces, we speed up the mixed-signal simulation by reducing
the number of necessary calculations. For situations where the
device is only connected to other digital nodes, the buffers have
no effect on the simulation.
The D0_GATE, shown in the listing, is a zero-delay primitive
gate timing model. For most TTL modeling applications, this
only serves as a place holder and is not an active part of the
model. Its function has been replaced by the PINDLY primitive.
The D0_GATE model can be found in the library file
dig_io.lib. For a more detailed description of digital