User`s guide

7
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26 Di
g
ital Device Modelin
g
The DtoA interface subcircuit format is shown here:
.SUBCKT DTOA < name suffix >
+ <
digital input node > < analog output node >
+ <
digital power supply node > < digital
+ ground node
>
+ PARAMS: DRVL=<
0 level driving resistance >
+ DRVH=<
1 level driving resistance >
+ CAPACITANCE=<
output load value >
+ {
N device, loading capacitor, and other
+ declarations
}
.ENDS
It also has four nodes. Unlike the AtoD subcircuit, the DtoA
subcircuit has three parameters. PSpice A/D will pass the values
of the I/O Model parameters DRVL, DRVH, and OUTLD to the
interface subcircuit’s DRVL, DRVH, and CAPACITANCE
parameters when it is called.
The library file
dig_io.lib
contains the I/O Models and
interface subcircuits for all logic families supported in the model
libraries. You should refer to this file for examples of the I/O
Models, interface subcircuits, and the proper use of N and O
devices.
Shown below are the I/O Model and AtoD interface subcircuit
definition used by the primitives describing the 74393 part.
.model IO_STD uio (
+ drvh=96.4 drvl=104
+ AtoD1="AtoD_STD" AtoD2="AtoD_STD_NX"
+ AtoD3="AtoD_STD" AtoD4="AtoD_STD_NX"
+ DtoA1="DtoA_STD" DtoA2="DtoA_STD"
+ DtoA3="DtoA_STD" DtoA4="DtoA_STD"
+ tswhl1=1.373ns tswlh1=3.382ns
+ tswhl2=1.346ns tswlh2=3.424ns
+ tswhl3=1.511ns tswlh3=3.517ns
+ tswhl4=1.487ns tswlh4=3.564ns
+)
.subckt AtoD_STD A D DPWR DGND
+ params: CAPACITANCE=0
*
O0 A DGND DO74 DGTLNET=D IO_STD
C1 A 0 {CAPACITANCE+0.1pF}
.ends