User`s guide

7
-
12 Di
g
ital Device Modelin
g
typical low-to-high propagation delay on a gate is specified as
the parameter TPLHTY. The minimum data-to-clock setup time
on a flip-flop is specified as the parameter TSUDCLKMN.
Several timing models are used by digital device 74393 from the
model libraries. One of them, D_393_1, is shown below for an
edge-triggered flip-flop.
.model D_393_1 ueff (
+ tppcqhlty=18ns tppcqhlmx=33ns
+ tpclkqlhty=6ns tpclkqlhmx=14ns
+ tpclkqhlty=7ns tpclkqhlmx=14ns
+ twclkhmn=20ns twclklmn=20ns
+ twpclmn=20ns tsudclkmn=25ns
+)
When creating your own digital device models, you can create
Timing Models like these for the primitives you are using.
MicroSim recommends that you save these in your own custom
model library, which you can then configure for use with a given
schematic.
One or more parameters may be missing from the Timing Model
definition. Data books do not always provide all three
(minimum, typical, and maximum) timing specifications. The
way the simulator handles missing parameters depends on the
type of parameter.
Treatment of unspecified propa
g
ation dela
y
s
Often, only the typical and maximum delays are specified in
data books. If, in this case, the simulator were to assume that the
unspecified minimum delay defaults to zero, the logic in certain
circuits could break down.
For this reason, the simulator provides two configurable options,
DIGMNTYSCALE and DIGTYMXSCALE, which are used to
extrapolate unspecified propagation delays in the Timing
Models.
For a description of Timin
g
Model parameters, see the
specific primitive type under U
devices in the online
MicroSim
PSpice A/D Reference Manual
.
Note
This discussion applies
only to propa
g
ation delay
parameters (TP). All other
timin
g
parameters, such as
setup/hold times and pulse
widths are handled differently,
and are discussed in the
followin
g
section.
These options are provided
under the Setup Command in the
Analysis menu in Schematics.