User`s guide

7
-
4 Di
g
ital Device Modelin
g
Tristate Gates
BUF3
INV3
AND3
NAND3
OR3
NOR3
XOR3
NXOR3
BUF3A
INV3A
AND3A
NAND3A
OR3A
NOR3A
XOR3A
NXOR3A
buffer
inverter
AND gate
NAND gate
OR gate
NOR gate
exclusive OR gate
exclusive NOR gate
buffer array
inverter array
AND gate array
NAND gate array
OR gate array
NOR gate array
exclusive OR gate array
exclusive NOR gate array
Bidirectional Transfer Gates
NBTG
PBTG
N-channel transfer gate
P-channel transfer gate
Flip-Flops and Latches
JKFF
DFF
SRFF
DLTCH
J-K, negative-edge triggered
D-type, positive-edge triggered
S-R gated latch
D gated latch
Pullup/Pulldown Resistors
PULLUP
PULLDN
pullup resistor array
pulldown resistor array
Delay Lines
DLYLINE delay line
Table 7-1
Digital Primitives Summary (continued)
Type Description