MicroSim PSpice A/D & Basics+ Circuit Analysis Software User’s Guide MicroSim Corporation 20 Fairbanks Irvine, California 92618 (714) 770-3022
Version 8.0, June, 1997. Copyright 1997, MicroSim Corporation. All rights reserved. Printed in the United States of America. TradeMarks Referenced herein are the trademarks used by MicroSim Corporation to identify its products. MicroSim Corporation is the exclusive owners of “MicroSim,” “PSpice,” “PLogic,” “PLSyn.
Contents Before You Begin Welcome to MicroSim . . . . . . . . . . . . . . . . . MicroSim PSpice A/D Overview . . . . . . . . . . . How to Use this Guide . . . . . . . . . . . . . . . . . Typographical Conventions . . . . . . . . . . . . Related Documentation . . . . . . . . . . . . . . . . Online Help . . . . . . . . . . . . . . . . . . . . If You Don’t Have the Standard PSpice A/D Package If You Have PSpice A/D Basics+ . . . . . . . . . If You Have the Evaluation CD-ROM . . . . . . What’s New . . . . . .
iv Contents Files Needed for Simulation . . . . . . . . . . . . . . . Files That Schematics Generates . . . . . . . . . . Netlist file . . . . . . . . . . . . . . . . . . . . Circuit file . . . . . . . . . . . . . . . . . . . . Other Files That You Can Configure for Simulation Model library . . . . . . . . . . . . . . . . . . Stimulus file . . . . . . . . . . . . . . . . . . . Include file . . . . . . . . . . . . . . . . . . . . Configuring model library, stimulus, and include files . . . . . . . . . . . .
Contents v Part Two Design Entry Chapter 3 Preparing a Schematic for Simulation Chapter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . Checklist for Simulation Setup . . . . . . . . . . . . . . . . . . . . Typical Simulation Setup Steps . . . . . . . . . . . . . . . . . . Advanced Design Entry and Simulation Setup Steps . . . . . . . When Netlisting Fails or the Simulation Does Not Start . . . . . . . . . . . . . . . . . . . . . . Things to check in your schematic . . . . . . . . . . . . .
vi Contents Missing Ground . . . . . . Check for this . . . . . Missing DC Path to Ground Check for this . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . What Are Models? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents vii Entering data sheet information . . . . . . . . . . . . . Extracting model parameters . . . . . . . . . . . . . . Adding curves for more than one temperature . . . . . Completing the model definition . . . . . . . . . . . . Using the Model Editor . . . . . . . . . . . . . . . . . . . . . Changing Model Properties . . . . . . . . . . . . . . . . . Editing .MODEL definitions . . . . . . . . . . . . . . Editing .SUBCKT definitions . . . . . . . . . . . . . . Changing the model name . . . . . . .
viii Contents Using the Symbol Wizard . . . . . . . . . . . . . How to Start the Symbol Wizard . . . . . . . How the Symbol Wizard Works . . . . . . . . Creating AKO Symbols . . . . . . . . . . . . . . What Are Base vs. AKO Symbols? . . . . . . Base and AKO Symbols in Symbol Libraries . How to Create AKO Symbols . . . . . . . . . Completing the Configuration of Your Part . . Using the Parts Utility to Create Symbols . . . . . Starting the Parts Utility . . . . . . . . . . . .
Contents ix Integrator and Differentiator . . . . . . . . . . . . . . . Table Look-Up Parts . . . . . . . . . . . . . . . . . . . Laplace Transform Part . . . . . . . . . . . . . . . . . . Math Functions . . . . . . . . . . . . . . . . . . . . . . ABM Expression Parts . . . . . . . . . . . . . . . . . . An Instantaneous Device Example: Modeling a Triode . PSpice A/D-Equivalent Parts . . . . . . . . . . . . . . . . . Implementation of PSpice A/D-Equivalent Parts . . . . .
x Contents Defining Output Strengths . . . . . . . . . . . . . . . . . . . . . . . Configuring the strength scale . . . . . . . . . . . . . . . . . . . Determining the strength of a device output . . . . . . . . . . . Controlling overdrive . . . . . . . . . . . . . . . . . . . . . . . Charge Storage Nets . . . . . . . . . . . . . . . . . . . . . . . . . . Creating Your Own Interface Subcircuits for Additional Technologies . . . . . . . . . . . . . . . . . . .
Contents xi Overview of DC Sweep . . . . . . . . . . . . . . . . . . . . . . . . . Setting Up a DC Stimulus . . . . . . . . . . . . . . . . . . . . . . . . Nested DC Sweeps . . . . . . . . . . . . . . . . . . . . . . . . . . . Curve Families for DC Sweeps . . . . . . . . . . . . . . . . . . . . . Bias Point Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Minimum Requirements to Run a Bias Point Detail Analysis . . . . . Overview of Bias Point Detail . . . . . . . . . . . . . . . . . .
xii Contents Minimum program setup requirements . . . . . . . . . Defining a Time-Based Stimulus . . . . . . . . . . . . . . . . Overview of Stimulus Generation . . . . . . . . . . . . . . The Stimulus Editor Utility . . . . . . . . . . . . . . . . . . . Stimulus Files . . . . . . . . . . . . . . . . . . . . . . . . Configuring Stimulus Files . . . . . . . . . . . . . . . . . Starting the Stimulus Editor . . . . . . . . . . . . . . . . . Defining Stimuli . . . . . . . . . . . . . . . . . . . . . . .
Contents xiii Chapter 13 Monte Carlo and Sensitivity/Worst-Case Analyses Chapter Overview . . . . . . . . . . . . . . . . . . . . . . . . Statistical Analyses . . . . . . . . . . . . . . . . . . . . . . . Overview of Statistical Analyses . . . . . . . . . . . . . . Output Control for Statistical Analyses . . . . . . . . . . . Model Parameter Values Reports . . . . . . . . . . . . . . Waveform Reports . . . . . . . . . . . . . . . . . . . . . Collating Functions . . . . . . . . . . . . . . . . . . . . .
xiv Contents Chapter 14 Digital Simulation Chapter Overview . . . . . . . . . . . . . . . . . . . . . What Is Digital Simulation? . . . . . . . . . . . . . . . . Steps for Simulating Digital Circuits . . . . . . . . . . . . Concepts You Need to Understand . . . . . . . . . . . . States . . . . . . . . . . . . . . . . . . . . . . . . . . Strengths . . . . . . . . . . . . . . . . . . . . . . . . Defining a Digital Stimulus . . . . . . . . . . . . . . . . Using Top-Level Interface Ports . . . . . . . . . . .
Contents xv Setting the Default A/D Interface . . . . . . . . . . . . . . . . . . . . Specifying Digital Power Supplies . . . . . . . . . . . . . . . . . . . . . Default Power Supply Selection by PSpice A/D . . . . . . . . . . . . Creating Custom Digital Power Supplies . . . . . . . . . . . . . . . . Overriding CD4000 power supply voltage throughout a schematic Creating a secondary CD4000, TTL, or ECL power supply . . . . Interface Generation and Node Names . . . . . . . . . . . . . . . . . . . . . . . .
xvi Contents Other Ways to Run Probe . . . . . . . . . . . . . . . . . . . . . . . . Starting Probe during a simulation . . . . . . . . . . . . . . . . . Pausing a simulation and then running Probe . . . . . . . . . . . . Interacting with Probe while in monitor mode . . . . . . . . . . . Using Schematic Markers to Add Traces . . . . . . . . . . . . . . . . Limiting Probe Data File Size . . . . . . . . . . . . . . . . . . . . . . Limiting file size using markers . . . . . . . . . . . . . . . . . . .
Contents xvii Rules for numeric values suffixes . . . . . . . . . . . . . . . . . . 17-56 Digital Trace Expressions . . . . . . . . . . . . . . . . . . . . . . . . . 17-57 Viewing Results Chapter 18 on the Schematic Chapter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing Bias Point Voltages and Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How it works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . If you run more than one analysis type . .
xviii Contents Appendix ASetting Initial State Appendix Overview . . . Save and Load Bias Point Save Bias Point . . . Load Bias Point . . . Setpoints . . . . . . . . . Setting Initial Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures Figure 1-1 Figure 1-2 Figure 1-3 Figure 1-4 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 2-7 Figure 2-8 Figure 2-9 Figure 2-10 Figure 2-11 Figure 2-12 Figure 2-13 Figure 2-14 Figure 2-15 Figure 2-16 Figure 2-17 Figure 2-18 Figure 2-19 Figure 2-20 Figure 2-21 Figure 2-22 Figure 2-23 Figure 2-24 Figure 2-25 Figure 4-1 Figure 4-2 Simulation Design Flow . . . . . . . . . . . . . . . . . . . . Schematics-Generated Data Files That PSpice A/D Reads . .
xx Figures Figure 4-3 Figure 4-4 Figure 4-5 Figure 4-6 Figure 4-7 Figure 4-8 Figure 4-9 Figure 5-1 Figure 6-1 Figure 6-2 Figure 6-3 Figure 6-4 Figure 6-5 Figure 6-6 Figure 6-7 Figure 6-8 Figure 6-9 Figure 6-10 Figure 6-11 Figure 6-12 Figure 6-13 Figure 6-14 Figure 6-15 Figure 6-16 Figure 6-17 Figure 6-18 Figure 6-19 Figure 6-20 Figure 7-1 Figure 7-2 Figure 8-1 Figure 9-1 Figure 9-2 Figure 9-3 Figure 9-4 Figure 9-5 Figure 10-1 Figure 10-2 Figure 11-1 Figure 11-2 Parts Utility Window with Data for a Bipola
Figures Figure 11-3 Figure 11-4 Figure 11-5 Figure 11-6 Figure 12-1 Figure 12-2 Figure 12-3 Figure 12-4 Figure 12-5 Figure 12-6 Figure 12-7 Figure 13-1 Figure 13-2 Figure 13-3 Figure 13-4 Figure 13-5 Figure 13-6 Figure 13-7 Figure 13-8 Figure 13-9 Figure 13-10 Figure 13-11 Figure 13-12 Figure 13-13 Figure 13-14 Figure 13-15 Figure 13-16 Figure 13-17 Figure 13-18 Figure 14-1 Figure 14-2 Figure 14-3 Figure 15-1 Figure 15-2 Figure 16-1 Figure 16-2 Figure 16-3 Figure 16-4 Figure 16-5 Figure 16-6 Figure 16-7 Fi
xxii Figures Figure 16-9 Figure 16-10 Figure 16-11 Figure 16-12 Figure 16-13 Figure 16-14 Figure 16-15 Figure 17-1 Figure 17-2 Figure 17-3 Figure 17-4 Figure 17-5 Figure 17-6 Figure 17-7 Figure 17-8 Figure 17-9 Figure 17-10 Figure 17-11 Figure 17-12 Figure A-1 Cumulative Ambiguity Hazard Example 2 . . . . . . . . . . . . . . Cumulative Ambiguity Hazard Example 3 . . . . . . . . . . . . . . Reconvergence Hazard Example 1 . . . . . . . . . . . . . . . . . . . Reconvergence Hazard Example 2 . . . . . . . .
Tables Table 1-1 Table 1-2 Table 1-3 Table 1-4 Table 1-5 Table 2-1 Table 3-1 Table 3-2 Table 3-3 Table 4-1 Table 4-2 Table 5-1 Table 6-1 Table 6-2 Table 6-3 Table 6-4 Table 6-5 Table 7-1 Table 7-2 Table 8-1 Table 8-2 Table 8-3 Table 8-4 Table 8-5 Table 8-6 Table 8-7 Table 9-1 Table 9-2 Table 11-1 Table 12-1 Table 13-1 Table 14-1 DC Analysis Types . . . . . . . . . . . . . . . . . . . AC Analysis Types . . . . . . . . . . . . . . . . . . . Time-Based Analysis Types . . . . . . . . . . . . . . .
xxiv Tables Table 14-2 Table 14-3 Table 14-4 Table 14-5 Table 14-6 Table 15-1 Table 15-2 Table 15-3 Table 15-4 Table 17-1 Table 17-2 Table 17-3 Table 17-4 Table 17-5 Table 17-6 Table 17-7 Table 17-8 Table 17-9 Table 17-10 Table 17-11 Table 17-12 Table 17-13 STIMn Part Attributes . . . . . . . . . . . . . . . . . FILESTIM Part Attributes . . . . . . . . . . . . . . . Simulation Condition Messages—Timing Violations . Simulation Condition Messages—Hazards . . . . . .
Before You Begin Welcome to MicroSim Welcome to the MicroSim family of products. Whichever programs you have purchased, we are confident that you will find that they meet your circuit design needs. They provide an easy-to-use, integrated environment for creating, simulating, and analyzing your circuit designs from start to finish.
xxvi Before You Begin MicroSim PSpice A/D Overview MicroSim PSpice A/D can simulate analog-only, mixed analog/ digital, and digital-only circuits. PSpice A/D’s analog and digital algorithms are built into the same program so that mixed analog/digital circuits can be simulated with tightly-coupled feedback loops between the analog and digital sections without any performance degradation. Once you prepare a schematic for simulation, MicroSim Schematics generates a circuit file set.
How to Use this Guide How to Use this Guide This guide is designed so you can quickly find the information you need to use PSpice A/D. This guide assumes that you are familiar with Microsoft Windows (NT or 95), including how to use icons, menus, and dialog boxes. It also assumes you have a basic understanding about how Windows manages applications and files to perform routine tasks, such as starting applications and opening, and saving your work.
xxviii Before You Begin Related Documentation Documentation for MicroSim products is available in both hard copy and online. To access an online manual instantly, you can select it from the Help menu in its respective program (for example, access the Schematics User’s Guide from the Help menu in Schematics). Note The documentation you receive depends on the software configuration you have purchased. The following table provides a brief description of those manuals available in both hard copy and online.
Related Documentation xxix The following table provides a brief description of those manuals available online only. This online manual... Provides this... MicroSim PSpice A/D Online Reference Manual Reference material for PSpice A/D. Also included: detailed descriptions of the simulation controls and analysis specifications, start-up option definitions, and a list of device types in the analog and digital model libraries.
xxx Before You Begin If You Don’t Have the Standard PSpice A/D Package If You Have PSpice A/D Basics+ PSpice A/D Basics+ provides the basic functionality needed for analog and mixed-signal design without the advanced features in the full PSpice A/D package. Because this guide is for both PSpice A/D Basics+ and PSpice A/D users, there are some features described here that are not available to PSpice A/ D Basics+ users.
If You Don’t Have the Standard PSpice A/D Package Feature PSpice A/D (Standard) xxxi PSpice A/D Basics+ Notable PSpice analysis and simulation features DC sweep, AC sweep, transient analysis yes yes noise, Fourier, temperature analysis yes yes parametric analysis yes no Note For expert PSpice A/D users, these are the PSpice circuit file commands that are not available in the Basics+ package: Monte Carlo, sensitivity/worst-case analysis yes no • .
xxxii Before You Begin Feature PSpice A/D (Standard) PSpice A/D Basics+ Notable PSpice devices and library models, continued digital primitives all most** digital model library 1600+ 1600+ MicroSim PCBoards yes yes MicroSim PSpice Optimizer yes no MicroSim PLSyn yes no Device Equations yes no network licensing yes no yes yes Purchase options Miscellaneous specifications unlimited circuit size *.
If You Don’t Have the Standard PSpice A/D Package If You Have the Evaluation CD-ROM MicroSim’s evaluation CD-ROM has the following limitations: • schematic capture limited to one schematic page (A or A4 size) • maximum of 50 symbols can be placed on a schematic • maximum of 10 symbol libraries can be configured • maximum of 20 symbols in a user-created symbol library • maximum of 70 parts can be netlisted • circuit simulation limited to circuits with up to 64 nodes, 10 transistors, two operation
xxxiv Before You Begin What’s New To find out more, see Chapter 18,Viewing Results on the Schematic. To find out more, see Using the Symbol Wizard on page 5-6. Bias information display on your schematic After simulating, you can display bias point information on your schematic so you can quickly zero in on problem areas in your design. This means you can selectively display voltages on wire segments and currents on device pins.
What’s New BSIM3 version 3 MOSFET model The BSIM3 version 3 model, which was developed at U.C. Berkeley, is a deep submicron MOSFET model with the same physical basis as the BSIM3 version 2 model, but with several major enhancements. These enhancements include: • A single I-V expression to describe current and output conductance in all regions of device operation. • Better modeling of narrow width devices. • A reformulated capacitance model to improve short and narrow geometry models.
Part One Simulation Primer Part One provides basic information about circuit simulation including examples of common analyses. Chapter 1,Things You Need to Know, provides an overview of the circuit simulation process including what PSpiceA/D does, descriptions of analysis types, and descriptions of important files. Chapter 2,Simulation Examples, presents examples of common analyses to introduce the methods and tools you’ll need to enter, simulate, and analyze your design.
Things You Need to Know 1 Chapter Overview This chapter introduces the purpose and function of the PSpice A/D circuit simulator. What is PSpice A/D? on page 1-2 describes PSpice A/D capabilities. Analyses You Can Run with PSpice A/D on page 1-3 introduces the different kinds of basic and advanced analyses that PSpice A/D supports. Using PSpice A/D with Other MicroSim Programs on page 1-8 presents the high-level simulation design flow.
1-2 Things You Need to Know What is PSpice A/D? Because the analog and digital simulation algorithms are built into the same program, PSpice A/D simulates mixed-signal circuits with no performance degradation because of tightly coupled feedback loops between the analog and digital sections. MicroSim PSpice A/D is a simulation program that models the behavior of a circuit containing any mix of analog and digital devices.
Analyses You Can Run with PSpice A/D Analyses You Can Run with PSpice A/D 1-3 See Chapter 2,Simulation Examples, for introductory examples showing how to run each type of analysis. See Part Three, Setting Up and Running Analyses, for a more Basic Analyses DC sweep & other DC calculations These DC analyses evaluate circuit performance in response to a direct current source. Table 1-1 summarizes what PSpice A/D calculates for each DC analysis type. Table 1-1 DC Analysis Types For this DC analysis...
1-4 Things You Need to Know AC sweep and noise These AC analyses evaluate circuit performance in response to a small-signal alternating current source. Table 1-2 summarizes what PSpice A/D calculates for each AC analysis type. Table 1-2 AC Analysis Types For this AC analysis... PSpice A/D computes this... AC sweep Small-signal response of the circuit (linearized around the bias point) when sweeping one or more sources over a range of frequencies.
Analyses You Can Run with PSpice A/D Transient and Fourier These time-based analyses evaluate circuit performance in response to time-varying sources. Table 1-3 summarizes what PSpice A/D calculates for each time-based analysis type. Table 1-3 Time-Based Analysis Types For this timebased analysis... Transient PSpice A/D computes this... Voltages, currents, and digital states tracked over time. For digital devices, you can set the propagation delays to minimum, typical, and maximum.
1-6 Things You Need to Know Advanced Multi-Run Analyses The multi-run analyses—parametric, temperature, Monte Carlo, and sensitivity/worst-case—result in a series of DC sweep, AC sweep, or transient analyses depending on which basic analyses you enabled. Parametric and temperature For parametric and temperature analyses, PSpice A/D steps a circuit value in a sequence that you specify and runs a simulation for each value. Table 1-4 shows the circuit values that you can step for each kind of analysis.
Analyses You Can Run with PSpice A/D Monte Carlo and sensitivity/worst-case Monte Carlo and sensitivity/worst-case analyses are statistical. PSpice A/D changes device model parameter values with respect to device and lot tolerances that you specify, and runs a simulation for each value. Table 1-5 summarizes how PSpice A/D runs each statistical analysis type. Table 1-5 For this statistical analysis... Statistical Analysis Types PSpice A/D does this...
1-8 Things You Need to Know Using PSpice A/D with Other MicroSim Programs Figure 1-1 illustrates the design flow for simulating a circuit and the programs that you use at each step.
Using PSpice A/D with Other MicroSim Programs Using Schematics to Prepare for Simulation Schematics is a design entry program you need to prepare your circuit for simulation. This means: • placing and connecting part symbols, • defining component values and other attributes, • defining input waveforms, • enabling one or more analyses, and • marking the points in the circuit where you want to see results.
1-10 Things You Need to Know not included in: What is the Parts Utility? The Parts utility is a model extractor that generates model definitions for PSpice A/D to use during simulation. All the Parts utility needs is information about the device found in standard data sheets. As you enter the data sheet information, the Parts utility displays device characteristic curves so you can verify the model-based behavior of the device.
Files Needed for Simulation Files Needed for Simulation To simulate your design, PSpice A/D needs to know about: • the parts in your circuit and how they are connected, • what analyses to run, • the simulation models that correspond to the parts in your circuit, and • the stimulus definitions to test with. This information is provided in various data files.
1-12 Things You Need to Know Netlist file Refer to the online MicroSim PSpice A/D Reference Manual for the syntax of the statements in the netlist file and the circuit file. The netlist file contains a list of device names, values, and how they are connected with other devices. The name that Schematics generates for this file is schematic_name.net. Circuit file The circuit file contains commands describing how to run the simulation.
Files Needed for Simulation Before starting simulation, PSpice A/D needs to read other files that contain simulation information for your circuit. These are model files, and if required, stimulus files and include files. You can create these files using MicroSim programs like the Stimulus Editor and the Parts utility. These programs automate file generation and provide graphical ways to verify the data. Or, you can use any text editor, like the MicroSim Text Editor, to enter the data manually.
1-14 Things You Need to Know Note Not all stimulus definitions require a stimulus file. In some cases, like DC and AC sources, you must use a schematic symbol and set its attributes. See What is not the Stimulus included Editor? on in: page 1-9 for a Stimulus file description. Include file A stimulus file contains time-based definitions for analog and/ or digital input waveforms.
Files That PSpice A/D Generates 1-15 Files That PSpice A/D Generates MicroSim Schematics MicroSim PSpice A/D simulation audit output file simulation results Probe data file Probe markers MicroSim Probe Figure 1-4 Data Files That PSpice A/D Creates After first reading the circuit file, netlist file, model libraries, and any other required inputs, PSpice A/D starts the simulation. As simulation progresses, PSpice A/D saves results to two files—the Probe data file and the PSpice output file.
1-16 Things You Need to Know PSpice output file The PSpice output file is an ASCII text file that contains: • the netlist representation of the circuit, • the PSpice command syntax for simulation commands and options (like the enabled analyses), • simulation results, and • warning and error messages for problems encountered during read-in or simulation.
Simulation Examples 2 Chapter Overview The examples in this chapter provide an introduction to the methods and tools for creating circuit designs, running simulations with PSpice A/D, and analyzing simulation results using Probe. All analyses are performed on the same example circuit to clearly illustrate analysis setup, simulation, and result analysis procedures for each analysis type.
2-2 Simulation Examples Example Circuit Creation This section describes how to use MicroSim Schematics to create the simple diode clipper circuit shown in Figure 2-1. Figure 2-1 Diode Clipper Circuit To open a new schematic window 1 Start Schematics. If Schematics is already running, be sure you are in the schematic editor.If you are in a blank schematic window (indicated by “Schematicn” in the title bar at the top of the window), you can begin creating the circuit.
Example Circuit Creation 4 Move the pointer to the correct position on the schematic (see Figure 2-1) and click to place the first source. 5 Move the cursor and click again to place the second source. 6 Right-click to cancel placement mode. 2-3 To place the diodes If needed, click to redisplay the Part Browser dialog box. 1 Go to the Part Browser dialog box. 2 In the Part name text box, type D1N39* to display a list of diodes. When placing components: 3 Click D1N3940.
2-4 Simulation Examples To connect the components 1 From the Draw menu, select Wire to enter wiring mode. The cursor changes to a pencil. 2 Click the connection point (the very end) of the pin on the bubble at the input of the circuit. 3 Click the nearest connection point of the input resistor R1. 4 Connect the other end of R1 to the output capacitor. 5 Connect the diodes to each other and to the wire between them: or press C+w You can right-click at any time to stop the wiring mode.
Example Circuit Creation 4 Continue naming devices until all circuit devices are named as in Figure 2-1 on page 2-2. To change the attribute values of devices 1 Double-click the attribute value (0V) of the VDC symbol, V1. 2 In the Set Attribute Value dialog box, type 5V. 3 Click OK. 4 Continue changing the attribute values of the circuit devices until all devices are named as in Figure 2-1 on page 2-2.
2-6 Simulation Examples Bias Point Analysis Running PSpice A/D When you perform a simulation, PSpice A/D generates an output file (for this example, clipper.out). PSpice A/D also generates bias information that Schematics can read and display. While PSpice A/D is running, the progress of the simulation appears and is updated in the PSpice A/D simulation status window (see Figure 2-3).
Bias Point Analysis 2-7 Using the Bias Information Display You can display bias information on your schematic, including voltages for all nets and currents into all pins. You can also control which nets and pins have voltage and current measurements displayed at any given time. To display bias voltage information at all nets 1 In Schematics, make the clipper.sch window active. 2 If the Simulation toolbar is not displayed, do the following: 3 a From the View menu, select Toolbars.
2-8 Simulation Examples To display bias current through V1, R2, and D1 1 In Schematics, make the clipper.sch window active. 2 On the Simulation toolbar, click the Enable Bias Current Display button. 3 From the Edit menu, select the Select All command. 4 On the Simulation toolbar, click the Show/Hide Currents on Selected Part(s) button. 5 Make sure that no schematic components are selected (by clicking a blank space on the schematic), then shift-click the V1, R2, and D1 symbols.
Bias Point Analysis 2-9 Using the Simulation Output File The simulation output file acts as an audit trail of the simulation. This file optionally echoes the contents of the circuit file as well as the results of the bias point calculation. If there are any syntax errors in the netlist declarations or simulation commands, or anomalies while performing the calculation, PSpice A/D writes error or warning messages to the output file.
2-10 Simulation Examples Note that the current through VIN is negative. By convention, PSpice A/D measures the current through a two terminal device into the first terminal and out of the second terminal. For voltage sources, current is measured from the positive terminal to the negative terminal; this is opposite to the positive current flow convention and results in a negative value in the output file. Finding Out More about Bias Point Calculations To find out more about this... See this...
DC Sweep Analysis 2-11 2 In the Analysis Setup dialog box, click the DC Sweep button. 3 Set up the DC Sweep dialog box as shown in Figure 2-6. Note The default settings for the DC Sweep dialog box are Voltage Source as the swept variable type and Linear as the sweep type. To choose a different swept variable type or sweep type, click the appropriate button. 4 Click OK to close the DC Sweep dialog box. 5 Click Close to exit the Analysis Setup dialog box. 6 From the File menu, select Save.
2-12 Simulation Examples Figure 2-7 Probe Plot 2 Click to place a marker on net Out (Figure 2-8). Figure 2-8 Clipper Circuit with Voltage Marker on Net Out Schematics saves markers with the schematic files. or press C+s 3 Right-click to cancel marker mode. 4 Activate the Probe window. The V(Out) waveform trace appears as shown in Figure 2-9. 5 From the File menu, select Save.
DC Sweep Analysis 2-13 trace legend Figure 2-9 Voltage at In, Mid, and Out To place cursors on V(In) and V(Mid) 1 In Probe, from the Tools menu, point to Cursor, then select Display. Two cursors appear for the first trace defined in the legend below the x-axis—V(In) in this example. The Probe Cursor window also appears. 2 To display the cursor crosshairs: a Position the mouse anywhere inside the plot window. b Click to display the crosshairs for the first cursor.
2-14 Simulation Examples 3 Your ability to get as close to 4.0 as possible depends on screen resolution and window size. 4 Place the first cursor on the V(In) waveform: a Click the portion of the V(In) trace in the proximity of 4 volts on the x-axis. The cursor crosshair appears, and the current X and Y values for the first cursor appear in the Probe Cursor window.
DC Sweep Analysis 2-15 Figure 2-12 shows the Probe window when both cursors are placed. There are also ways to display the difference between two voltages as a trace: • In Probe, add the trace expression V(In)-V(Mid). • In Schematics, from the Markers menu, select Mark Voltage Differential and place the two markers on different pins or wires. Figure 2-12 Voltage Difference at V(In) = 4 Volts To delete all of the traces 1 From the Trace menu, select Delete All.
2-16 Simulation Examples Transient Analysis This example shows how to run a transient analysis on the clipper circuit. This requires adding a time-domain voltage stimulus as shown in Figure 2-13. Figure 2-13 Diode Clipper Circuit with a Voltage Stimulus To add a time-domain voltage stimulus not included in: If you do not have the Stimulus Editor: 1 Place a VSIN symbol instead of VSTIM, then double click it. 2 Set values for the VOFF, VAMPL, and FREQ attributes as defined in step 13.
Transient Analysis 6 From the Edit menu, select Paste. 7 Place the ground symbol under the VSTIM symbol as shown in Figure 2-13. 8 From the View menu, select Fit. 9 From the File menu, select Save As, and then type clippert.sch as the name of the schematic file you want to save. 10 Double-click the VSTIM symbol. 11 In the Set Attribute Value dialog box, type SINE, then click OK. The New Stimulus dialog box and the Stimulus Editor appear. 12 In the Stimulus Editor, click SIN, then click OK.
2-18 Simulation Examples 15 Click OK. or press V+@ 16 From the File menu, select Save to save the stimulus information. 17 From the File menu, select Exit. To set up and run the transient analysis 1 In Schematics, from the Analysis menu, select Setup. 2 In the Analysis Setup dialog box, click Transient to display the Transient Analysis dialog box. 3 Set up the Transient dialog box as shown in Figure 2-15. 4 Click OK.
Transient Analysis 3 Click OK to display the traces. 4 Place the symbols shown in the trace legend on the traces themselves as shown in Figure 2-16: a From the Tools menu, select Options to display the Probe Options dialog box. b In the Use Symbols frame, click Always. c Click OK. 2-19 These waveforms illustrate the clipping of the input signal. Figure 2-16 Sinusoidal Input and Clipped Output Waveforms Finding Out More about Transient Analysis To find out more about this... See this...
2-20 Simulation Examples AC Sweep Analysis The AC sweep analysis in PSpice A/D is a linear (or small signal) frequency domain analysis that can be used to observe the frequency response of any circuit at its bias point. Setting Up and Running an AC Sweep Analysis In this example, you will set up the clipper circuit for AC analysis by adding an AC voltage source for a stimulus signal (Figure 2-17) and by setting up AC sweep parameters.
AC Sweep Analysis 2-21 4 In the Replace Part dialog box, type VAC. 5 Select ( ✓) the Keep Attribute Values check box. 6 Click OK. The input voltage source changes to an AC voltage source. 7 Double-click the displayed (AC) value of the new Vin. 8 In the Set Attribute Value dialog box, set the value to 1V. The new Vin still has a DC attribute that you can use to include a bias with the AC source. Double-click the AC source to see the DC attribute value.
2-22 Simulation Examples AC Sweep Analysis Results Probe displays the dB magnitude (20log10) of the voltage at the marked nets, Out and Mid, as shown in Figure 2-19. VDB(Mid) has a lowpass response due to the diode capacitances to ground. The output capacitance and load resistor act as a highpass filter, so the overall response, illustrated by VDB(out), is a bandpass response.
AC Sweep Analysis 2-23 6 From the Edit menu, select Cut. 7 From the Plot menu, select Add Y Axis. 8 From the Edit menu, select Paste. The Bode plot appears as shown in Figure 2-20. Figure 2-20 Bode Plot of Clipper’s Frequency Response Finding Out More about AC Sweep and Noise Analysis To find out more about this... See this...
2-24 Simulation Examples not included in: Parametric Analysis This example shows the effect of varying input resistance on the bandwidth and gain of the clipper circuit by: • Changing the value of R1 to the expression {Rval}. • Adding a PARAM symbol to declare the parameter Rval. • Specifying a parametric analysis to step the value of R1 using Rval. Figure 2-21 Clipper Circuit with Global Parameter Rval The example results in multiple analysis runs, each with a different value of R1.
Parametric Analysis 2-25 Setting Up and Running the Parametric Analysis To change the value of R1 to the expression {Rval} 1 In Schematics, open clippera.sch. 2 Double-click the value label for R1. 3 In the Set Attribute Value dialog box, type {Rval}. 4 Click OK. PSpice A/D interprets text in curly braces as an expression that evaluates to a numerical value. This example uses the simplest form of an expression— a constant.
2-26 Simulation Examples To set up and run a parametric analysis to step the value of R1 using Rval 1 From the Analysis menu, select Setup. 2 In the Analysis Setup dialog box, click Parametric. 3 Set up the Parametric dialog box as shown below. This setup specifies that the parameter Rval is to be stepped from 100 to 10k logarithmically with a resolution of 10 points per decade. The analysis is run for each value of Rval.
Parametric Analysis 2-27 Analyzing Waveform Families in Probe There are 21 analysis runs, each with a different value of R1. When Probe starts, it displays the Available Sections dialog box that lists all 21 runs and the Rval parameter value for each. You have the option to select one or more runs. If Probe is not set to run automatically after simulation, from the Analysis menu, select Run Probe.
2-28 Simulation Examples Note 4 or press I The difference in gain is apparent. You can also plot the difference of the waveforms for runs 21 and 1 and then use the search commands feature to find certain characteristics of the difference. Plot the new trace by specifying a waveform expression: a From the Trace menu, select Add.
Parametric Analysis Figure 2-24 Comparison of Small Signal Frequency Response at 100 and 10 kΩ Input Resistance Finding Out More about Parametric Analysis To find out more about this... See this...
2-30 Simulation Examples not included in: Probe Performance Analysis Performance analysis is an advanced feature in Probe that you can use to compare the characteristics of a family of waveforms. Performance analysis uses the principle of search commands introduced earlier in this chapter to define functions that detect points on each curve in the family.
Probe Performance Analysis 2-31 9 Click Next> or Finish. Probe displays a plot of the 3 dB bandwidth vs. Rval. 10 Change the x-axis to log scale. a From the Plot menu, select X Axis Settings. b In the Scale frame of the X Axis dialog box, choose Log. c Click OK. Double-click the x-axis. To plot gain vs. Rval manually 1 From the Plot menu, select Add Y Axis. 2 From the Trace menu, select Add.
2-32 Simulation Examples Finding Out More about Performance Analysis To find out more about this... See this...
Part Two Design Entry Part Two provides information about how to enter circuit designs that you want to simulate in MicroSim Schematics. Chapter 3,Preparing a Schematic for Simulation, outlines the things you need to do to successfully simulate your schematic including troubleshooting tips for the most frequently asked questions. Chapter 4,Creating and Editing Models, describes how to use the tools to create and edit model definitions, and how to configure the models for use.
Preparing a Schematic for Simulation 3 Chapter Overview This chapter provides introductory information to help you enter circuit designs that simulate properly. If you want an overview, use the checklist on page 3-2 to guide you to specific topics.
3-2 Preparing a Schematic for Simulation Checklist for Simulation Setup This section is provided so you can quickly step through what you need to do to set up your circuit for simulation. 1 Find the topic that is of interest in the first column of any of these tables. 2 Go to the referenced section. For those sections that provide overviews, you will find references to more detailed discussions. Typical Simulation Setup Steps For more information on this step... See this... To find out this...
Checklist for Simulation Setup For more information on this step... ✔ Place markers. See this... To find out this... Using Schematic Markers to Add Traces on page 17-13 How to display results in Probe by picking schematic nets. Limiting Probe Data File Size on page 17-15 How to limit the Probe data file size.
3-4 Preparing a Schematic for Simulation Advanced Design Entry and Simulation Setup Steps For more information on this step... ✔ Create new models. ✔ Create new symbols. See this... To find out how to... Chapter 4,Creating and Editing Models Define models using the Parts utility, model editor, or Create Subcircuit command. Chapter 6,Analog Behavioral Modeling Define the behavior of a block of analog circuitry as a mathematical function or lookup table.
Checklist for Simulation Setup To get online information about an error or warning shown in the Message Viewer 1 Select the error or warning message. 2 Press 1. The following tables list the most commonly encountered problems and where to find out more about what to do. Things to check in your schematic Make sure that... To find out more, see this... ✔ The model libraries, stimulus files, and include Configuring Model Libraries on page 4-41 files are configured. ✔ You are using symbols with models.
3-6 Preparing a Schematic for Simulation Things to check in your system configuration Make sure that... To find out more, see this... ✔ Path to the PSpice A/D and Probe programs is In your MicroSim Schematics User’s Guide: the Changing Application Settings section in the Using the Schematic Editor chapter correct. ✔ Directory containing your schematic file has Your operating system manual write permission. ✔ Your system has sufficient free memory and disk space.
Using Parts That You Can Simulate 3-7 Using Parts That You Can Simulate The MicroSim libraries supply numerous parts designed for simulation.
3-8 Preparing a Schematic for Simulation Vendor-Supplied Parts For a listing of vendor-supplied parts contained in the MicroSim libraries, refer to the online Library List. The MicroSim libraries provide an extensive selection of manufacturers’ analog and digital parts. Typically, the library name reflects the kind of parts contained in the library and the vendor that provided the models. To find out more about each model library, read the comments in the .lib file header. Example: motor_rf.
Using Parts That You Can Simulate 3-9 Notice the following: • There is a generic OP-27 symbol provided by MicroSim, the OP-27/AD from Analog Devices, Inc., and the OP-27/LT from Linear Technology Corporation. • The Model column for all of these parts contains an asterisk. This indicates that this part is modeled and that you can simulate it.
3-10 Preparing a Schematic for Simulation Note This method finds only parts that MicroSim supplies. To find parts using the online Library List 1 From the Help menu in Schematics, PSpice A/D, or the Parts utility, select Library List. 2 From the Library List Help topic, click the button for the analog, digital, or mixed-signal device types that you want to search. 3 From the Tools menu, select Find. 4 In the Find What text box, type the generic part name.
Using Parts That You Can Simulate 3-11 Passive Parts The MicroSim libraries supply several basic parts based on the passive device models built-in to PSpice A/D. These are summarized in the following table. These symbols are available... For this part type... Which is this PSpice device letter...
3-12 Preparing a Schematic for Simulation Breakout Parts To find out more about models, see What Are Models? on page 4-3. To find out more about Monte Carlo and sensitivity/worst-case analyses, see Chapter The MicroSim libraries supply passive and semiconductor parts with default model definitions that define a basic set of model parameters.
Using Parts That You Can Simulate 3-13 Behavioral Parts Behavioral parts allow you to define how a block of circuitry should work without having to define each discrete component. Analog behavioral parts These parts use analog behavioral modeling (ABM) to define each part’s behavior as a mathematical expression or lookup table.
3-14 Preparing a Schematic for Simulation Using Global Parameters and Expressions for Values In addition to literal values, you can use global parameters and expressions to represent numeric values in your circuit design. Global Parameters When multiple parts are set to the same value, global parameters provide a convenient way to change all of their values for “what-if” analyses.
Using Global Parameters and Expressions for Values 3-15 To declare a global parameter 1 Place a PARAM symbol in your schematic. 2 Double-click the PARAM symbol instance. 3 In the Attributes dialog box, declare up to three global parameters. For each global parameter: a Click the NAMEn attribute, type the parameter name in the Value text box, and then click Save Attr. b Click the corresponding VALUEn attribute, type a default value for the parameter in the Value text box, and then click Save Attr.
3-16 Preparing a Schematic for Simulation Expressions An expression is a mathematical relationship that you can use to define a numeric or boolean (TRUE/FALSE) value. PSpice A/D evaluates the expression to a single value every time: Example: A parameter that changes with each step of a DC sweep or parametric analysis. • it reads in a new circuit, and • a parameter value used within an expression changes during an analysis.
Using Global Parameters and Expressions for Values Note Though PSpice A/D accepts expressions of any length, Schematics does not. Value assignments to symbol attributes are limited to 1,024 characters. If your expression exceeds this limit, create a user-defined function (saved in an include file) and use the function in the expression. Remember to configure the include file. Table 3-1 Operators in Expressions This operator class... Includes this operator.. .
3-18 Preparing a Schematic for Simulation Table 3-2 Functions in Arithmetic Expressions Note In Probe, this function is D(x). This function... Means this...
Using Global Parameters and Expressions for Values Table 3-2 3-19 Functions in Arithmetic Expressions (continued) This function... Means this... SDT(x) time integral of x which is applicable to transient analysis only TABLE(x,x1,y1,...
3-20 Preparing a Schematic for Simulation Table 3-3 System Variables This variable... Note If a passive or semiconductor device has an independent temperature assignment, then TEMP does not represent that device’s temperature. To find out more about customizing temperatures for passive or semiconductor devices, refer to the .MODEL command in the Commands chapter in the online MicroSim PSpice A/D Reference Manual. TEMP Evaluates to this...
Defining Power Supplies 3-21 Defining Power Supplies For the Analog Portion of Your Circuit If the analog portion of your circuit requires DC power, then you need to include a DC source in your design. To specify a DC source, use one of the following symbols. For this source type... Use this symbol...
3-22 Preparing a Schematic for Simulation For this logic family... Use this symbol...
Defining Stimuli 3-23 Defining Stimuli To simulate your circuit, you need to connect one or more source symbols that describe the input signal that the circuit must respond to. The MicroSim libraries supply several source symbols that are described in the tables that follow.
3-24 Preparing a Schematic for Simulation If you want this kind of input... Use this symbol for voltage... piecewise-linear that repeats n times VPWL_N_TIMES or VPWL_F_N_TIMES** frequency-modulated sine wave VSFFM or VSTIM* sine wave VSIN or VSTIM* *. VSTIM and ISTIM symbols require the Stimulus Editor to define the input signal; these symbols are not available in Basics+. **.
Defining Stimuli 3-25 If you want to specify multiple stimulus types If you want to run more than one analysis type, including a transient analysis, then you need to use either of the following: • time-based stimulus symbols with AC and DC attributes • VSRC or ISRC symbols Using time-based stimulus symbols with AC and DC attributes The time-based stimulus symbols that you can use to define a transient, DC, and/or AC input signal are listed below.
3-26 Preparing a Schematic for Simulation Using VSRC or ISRC symbols The VSRC and ISRC symbols have one attribute for each analysis type: DC, AC, and TRAN. You can set any or all of them using PSpice netlist syntax. When you give them a value, the syntax you need to use is as follows. For the syntax and meaning of transient source specifications, refer to the I/V (independent current and voltage source) device type in the Analog Devices chapter in the online This attribute... Has this syntax...
Defining Stimuli *. The DIGSTIM, IF_IN and INTERFACE symbols require the Stimulus Editor to define the input signal; these symbols are not available in Basics+.
3-28 Preparing a Schematic for Simulation Things to Watch For For a roadmap to other commonly encountered problems and solutions, see When Netlisting Fails or the Simulation Does Not Start on page 3-4. This section includes troubleshooting tips for some of the most common reasons why your circuit might fail to netlist or simulate. Unmodeled Parts If you see messages like this in the Message Viewer, Warning: Part part_name has no simulation model.
Things to Watch For 3-29 Analog Libraries with Modeled Parts 1_SHOT EPWRBJT MOTOR_RF ABM FILTSUB NAT_SEMI ADV_LIN FWBELL OPAMP AMP HARRIS OPTO ANALOG IGBT* PHIL_BJT ANA_SWIT JBIPOLAR PHIL_FET ANLG_DEV JDIODE PHIL_RF ANL_MISC JFET POLYFET APEX JJFET PWRBJT BIPOLAR JOPAMP PWRMOS BREAKOUT JPWRBJT SIEMENS BUFFER JPWRMOS SWIT_RAV BURR_BRN LIN_TECH SWIT_REG CD4000 MAGNETIC* TEX_INST COMLINR MAXIM THYRISTR* DIODE MIX_MISC** TLINE* EBIPOLAR MOTORAMP XTAL EDIODE MO
3-30 Preparing a Schematic for Simulation Check for this if the part in question is custombuilt Are there blank (or inappropriate) values for the symbol’s MODEL and TEMPLATE attributes? If so, load this symbol into the symbol editor and set these attributes appropriately. One way to approach this is to edit the symbol that appears on your schematic.
Things to Watch For 3-31 Check for this • Does the relevant model library, stimulus file, or include file appear in the configuration list? • If the file is configured, does the default library search path include the directory path where the file resides, or explicitly define the directory path in the configuration list? If the file is not configured, add it to the list and make sure that it appears before any other library or file that has an identicallynamed definition.
3-32 Preparing a Schematic for Simulation unmodeled pins The MicroSim libraries include parts that are suitable for both simulation and board layout. These parts may have a mix of modeled pins (solid line) and unmodeled pins (broken line). The unmodeled pins map into packages but have no electrical significance; PSpice A/D ignores unmodeled pins during simulation.
Things to Watch For 3-33 Missing DC Path to Ground This applies to analog-only and mixed-signal circuits. If for selected nets in your circuit you see this message in the PSpice output file, ERROR -- Node node_name is floating. then you may be missing a DC path to ground.
Creating and Editing Models 4 Chapter Overview This chapter provides information about creating and editing models for parts that you want to simulate. Topics are grouped into four areas introduced later in this overview. If you want to find out quickly which tools to use to complete a given task and how to start, then: 1 Go to the roadmap in Ways to Create and Edit Models on page 4-8. 2 Find the task you want to complete.
4-2 Creating and Editing Models Background information These topics present model library concepts and an overview of the tools that you can use to create and edit models. Topics include: • What Are Models? on page 4-3 • How Are Models Organized? on page 4-4 • Tools to Create and Edit Models on page 4-7 Task roadmap This topic helps you find the sections in this chapter that are relevant to the model editing task that you want to complete.
What Are Models? 4-3 What Are Models? A model defines the electrical behavior of a part. On your schematic, this correspondence is defined by a symbol’s MODEL attribute, which is assigned the model name. A model is defined as either a: • model parameter set, or • subcircuit netlist, For a description of the MODEL attribute, see MODEL on page 5-19. depending on the device type that it describes. Both ways of defining a model are text-based with specific rules of syntax.
4-4 Creating and Editing Models Example: * FIRST ORDER RC STAGE .SUBCKT LIN/STG IN OUT AGND + PARAMS: C1VAL=1 C2VAL=1 R1VAL=1 R2VAL=1 + GAIN=10000 C1 IN N1 {C1VAL} C2 N1 OUT {C2VAL} R1 IN N1 {R1VAL} R2 N1 OUT {R2VAL} EAMP1 OUT AGND VALUE={V(AGND,N1)*GAIN} .ENDS How Are Models Organized? The key concepts behind model organization are as follows: • Model definitions are saved in files called libraries. • Model libraries must be configured so PSpice A/D searches them for definitions.
How Are Models Organized? 4-5 Model Library Configuration PSpice A/D searches model libraries for the model names specified by the MODEL attribute value on symbols in your schematic. These are the model definitions that PSpice A/D uses to simulate your circuit. For PSpice A/D to know where to look for these model definitions, you must configure the libraries. This means: • Specifying the directory path or paths to the model libraries.
4-6 Creating and Editing Models Nested Model Libraries Besides device model and subcircuit definitions, model libraries can also contain references to other model libraries using the PSpice .LIB syntax. When searching model libraries for matches, PSpice A/D also scans these referenced libraries. Example: Suppose you have two custom model libraries, mydiodes.lib and myopamps.lib, that you want PSpice A/ D to search any time you simulate a design. Then you can create a third model library, mymodels.
Tools to Create and Edit Models 4-7 Tools to Create and Edit Models There are three tools that you can use to create and edit model definitions. Use the: • • • Parts utility when you want to: • derive models from data sheet curves provided by manufacturers, or • modify the behavior of a Parts-supported model.
4-8 Creating and Editing Models Ways to Create and Edit Models This section is a roadmap to other information in this chapter. Find the task that you want to complete, then go to the referenced sections for more information. If you want to... Then do this... To find out more, see this... ➥ Create or edit the model Create or load the symbol first in the symbol editor, then edit the model using either the: Running the Parts Utility from the Symbol Editor on page 4-18.
Ways to Create and Edit Models * For a list of device types that the Parts utility supports, see Parts-Supported Device Types on page 4-12. If the Parts utility does not support the device type for the model definition that you want to create, then you can use a standard text editor to create a model definition using the PSpice .MODEL and .SUBCKT command syntax. Remember to configure the new model library.
4-10 Creating and Editing Models not included in: Using the Parts Utility to Edit Models The Parts utility converts information that you enter from the part manufacturer’s data sheet into either: The Parts utility does not support the following subcircuit constructs: • optional nodes construct, OPTIONAL: • variable parameters construct, PARAMS: • local .PARAM command • model parameter sets using PSpice .MODEL syntax, or • subcircuit netlists using PSpice .
Using the Parts Utility to Edit Models 4-11 Ways to Use the Parts Utility You can use the Parts utility five ways: • • • • • To define a new model, and then automatically create a symbol. Any new models and symbols are automatically available to any schematic. To find out more, see Running To define a new model only (no symbol). You can optionally turn off the symbol creation feature for new models.
4-12 Creating and Editing Models Parts-Supported Device Types Part types that the Parts utility models using the .MODEL statement are based on the models built into PSpice A/D. Note The model parameter defaults used by the Parts utility are different from those used by the models built into PSpice A/D. Table 4-1 summarizes the device types supported in the Parts utility. Table 4-1 Models Supported in the Parts Utility Uses this definition form... And this name prefix*... diode .
Using the Parts Utility to Edit Models 4-13 Ways To Characterize Models Figure 4-2 shows two ways to characterize models using the Parts utility. Each curve in the Parts utility is defined only by the parameters being adjusted. For the diode, the forward current curve only shows the part of the current equation which is associated with the forward characteristic parameters (such as IS, N, Rs).
4-14 Creating and Editing Models Analyzing the effect of model parameters on device characteristics You can also edit model parameters directly and investigate how changing their values affects a device characteristic. As you change model parameters, the Parts utility recalculates the behavior of the part characteristics and displays a new curve for each of the affected ones.
Using the Parts Utility to Edit Models 4-15 To fit the model 1 2 For each device characteristic that you want to set up: a In the Model Spec list, select the device characteristic. b From the Edit menu, select Spec. c In the Edit Model Spec dialog box, type in the device information from the data sheet. d Click Add. e Click OK. From the Extract menu, select Parameters to extract all relevant model parameters for the current specification.
4-16 Creating and Editing Models After you have selected the part that you want to model, you can proceed with entering data sheet information and model fitting as described in How to Fit Models on page 4-14.
Using the Parts Utility to Edit Models 2 If not already checked, select Always Create Symbol to enable automatic symbol creation. 3 In the Save Symbol To frame, define the name of the symbol library for the new symbol. Choose either: • Symbol Library Path Same As Model Library to create or open the .slb file that has the same name prefix as the currently open model library (.lib). • User-Defined Symbol Library, and then enter a file name into the Symbol Library Name text box.
4-18 Creating and Editing Models After you have started the Parts utility, you can proceed with entering data sheet information and model fitting as described in How to Fit Models on page 4-14. Running the Parts Utility from the Symbol Editor If you want to: • base a new part on an existing symbol, or • edit the model for an existing symbol and have it affect all schematics that use the symbol, then run the Parts utility from the symbol editor in Schematics.
Using the Parts Utility to Edit Models The symbol editor searches the model libraries for the model. • If found, the symbol editor opens the model library containing the original model and initializes Parts with the model information. • If not found, the symbol editor assumes that it is a new model; at startup, the Parts utility displays the Create New Part dialog box. 4-19 To find out how Schematics searches the library, see Changing Model Library Search Order on page 4-45.
4-20 Creating and Editing Models Once you have started the Parts utility, you can proceed with entering data sheet information and model fitting as described in How to Fit Models on page 4-14. Running the Parts Utility from the Schematic Editor If you want to: • test behavior variations on a part, or • refine a model before making it available to all schematics, then run the Parts utility from the schematic editor in Schematics. This means editing models for part instances on your schematic.
Using the Parts Utility to Edit Models 4-21 Starting the Parts utility To start editing an instance model 1 In the schematic editor, select one symbol on your schematic. 2 From the Edit menu, select Model. 3 Click Edit Instance Model (Parts). The schematic editor searches the model libraries for the instance model.
4-22 Creating and Editing Models What happens if you don’t save the instance model Before the schematic editor starts the Parts utility, it does these things: • Makes a copy of the original model and saves it as an instance model in schematic_name.lib. • Configures schematic_name.lib for local use, if not already done. • Assigns the new instance model name to the MODEL attribute for the selected part instance.
Using the Parts Utility to Edit Models The Parts Utility Tutorial In this tutorial, you will model a simple diode device as follows: • Create the schematic for a simple half-wave rectifier. • Run the Parts utility from the schematic editor to create an instance model for the diode in your schematic. Creating the half-wave rectifier schematic To draw the schematic 1 Start Schematics. 2 From the Draw menu in the schematic editor, select Get New Part.
4-24 Creating and Editing Models Starting the Parts utility for the D1 diode To start the Parts utility 1 Click the D1 symbol to select it. 2 From the Edit menu, select Model. 3 Click Edit Instance Model (Parts). The schematic editor searches the configured set of model libraries for an instance model corresponding to this symbol. 4 Click OK. Three things happen: • Schematics automatically creates rectfr.lib and configures it into the set of local model libraries. • The Parts window displays.
Using the Parts Utility to Edit Models You can modify each model characteristic listed in the Model Spec list with new values from the data sheets. The Part utility takes the new information and fits new model parameter values. When updating the entered data, the Parts utility expects either: • device curve data (point pairs), or • single-valued data, depending on the device characteristic. For the diode, Forward Current, Junction Capacitance, and Reverse Leakage require device curve data.
4-26 Creating and Editing Models To change the Forward Current characteristic 1 In the Model Spec list, double-click Forward Current. The Edit Model Spec-Forward Current dialog box appears. This dialog box requires curve data. 2 In the Vfwd text box, type 1.3. 3 Press F to move to the Ifwd text box, and then type 0.2. 4 Click Add. The new values appear in the Vfwd-Ifwd table. 5 Click OK.
Using the Parts Utility to Edit Models 4-27 Extracting model parameters To generate new model parameter values 1 From the Extract menu, select Parameter. The new values appear in the Parameters box with an asterisk appearing to the right of the ones that have changed. To display the curves for the five diode characteristics 1 Click Forward Current and drag the mouse down to the end of the list to select all of the entries in the Model Spec box. 2 From the Plot menu, select Display.
4-28 Creating and Editing Models Adding curves for more than one temperature By default, the Parts utility computes device curves at 27°C. For any characteristic, you can add curves to the plot at other temperatures. To add curves for Forward Current at a different temperature press Z 1 Click the Forward Current plot window to bring it to the foreground. 2 From the Trace menu, select Add. 3 Type 100 (in °C). 4 Click OK. The Forward Current plot should appear as shown in Figure 4-7.
Using the Model Editor 4-29 Completing the model definition You can refine the model definition by: • modifying the entered data as described before, or • editing model parameters directly. Example: If you double-click BV in the Parameters list, the Edit Parameter BV dialog box displays. You can update individual model parameters by double-clicking the entry in the Parameters list of the main parts window, and then updating the parameter values in the dialog box.
4-30 Creating and Editing Models Changing Model Properties To find out more about PSpice A/ D command and netlist syntax, refer to the online MicroSim PSpice A/D Reference Manual. The model editor window contains an edit area that displays the PSpice commands and netlist entries for the model definition. You can freely edit the definition just as you would in any standard text editor. Editing .MODEL definitions For definitions implemented as model parameter sets using PSpice .
Using the Model Editor 4-31 Editing .SUBCKT definitions For definitions implemented as subcircuit netlists using PSpice .SUBCKT syntax, the model editor displays the subcircuit syntax exactly as it appears in the model library. The model editor also includes all of the comments immediately before or after the subcircuit definition. Changing the model name You can change the model name directly in the PSpice .MODEL or .
4-32 Creating and Editing Models Once you have started the model editor, you can proceed to change the text as described in Start the model editor. 2 Create or load a symbol definition. Changing Model Properties on page 4-30. 3 From the Edit menu, click Attribute. a Make sure that your symbol has a MODEL attribute and an assigned value. b Change the PART attribute value as needed to match the model name. c Click OK. 4 From the Edit menu, select Model. 5 Click Edit Model (Text).
Using the Model Editor 4-33 Running the Model Editor from the Schematic Editor If you want to: • define tolerances on model parameters for statistical analyses, • test behavior variations on a part, or • refine a model before making it available to all schematics, You can also use the model editor to view the syntax for a model definition. When you are finished, be sure to click Cancel so the schematic editor does not create an instance model.
4-34 Creating and Editing Models Starting the model editor Once you have started the model editor, you can proceed to change the text as described in To start editing an instance model Changing Model Properties on page 4-30. 1 In the schematic editor, select the symbol on your schematic. 2 From the Edit menu, select Model. 3 Click Edit Instance Model (Text).
Using the Model Editor Example: Editing a Q2N2222 Instance Model Suppose you have a schematic named my.sch that contains several instances of a Q2N2222 bipolar transistor. Suppose also, that you are interested in the effect of base resistance variation on one specific device—Q6. To do this you need to do the following: • Define a tolerance (in this example, 5%) on the Rb model parameter. • Set up and run a Monte Carlo analysis. The following example demonstrates how to set up the instance model for Q6.
4-36 Creating and Editing Models Figure 4-9 shows how the model definition looks after having made these changes. Figure 4-9 Model Editor Showing Q2N2222 with a DEV Tolerance Set on Rb Saving the edits and updating the schematic If you were to verify the model library configuration (from the Analysis menu in the schematic editor, select Library and Include Files), you would see entries for nom.lib* (global as denoted by the asterisk) and my.lib (local, no asterisk) in the model library list.
Using the Create Subcircuit Command Using the Create Subcircuit Command The Create Subcircuit command in the schematic editor creates a subcircuit netlist definition for the displayed level of hierarchy and all lower levels in your schematic. The schematic editor does the following things for you: • Maps any named interface ports at the active level of hierarchy to terminal nodes in the PSpice .SUBCKT statement. • Writes the subcircuit definition to a file named schematic_name.sub.
4-38 Creating and Editing Models schematic_name.sub as either a model library or include file (see Configuring Model Libraries on page 4-41). Refinements can include extending the subcircuit definition using the optional nodes construct, OPTIONAL:, the variable parameters construct, PARAMS:, and the .FUNC and local .PARAM commands. 7 If necessary, refine the subcircuit definition for the new symbol or for a part instance on your schematic using the model editor (see Using the Model Editor on page 4-29).
Reusing Instance Models 5 In the Model Name text box, type the name of the existing model that you want to use. 6 Click OK. 4-39 To change the model reference for a symbol in the symbol library 1 Find the name of the model that you want to use. 2 In the schematic editor, from the File menu, select Edit Library to start the symbol editor. Or you can replace steps 2-4 as follows: 3 From the File menu, select Open, and then select the symbol library that contains the symbol that you want to change.
4-40 Creating and Editing Models Reusing Instance Models in the Same Schematic There are two ways to use the instance model elsewhere in the same schematic. To use the instance model elsewhere on your schematic 1 See Changing the Model Reference to an Existing Model Definition on page 4-38. Do one of the following: • Change the model reference for other part instances to the name of the new model instance. • From the Edit menu, use Copy and Paste to place more part instances.
Configuring Model Libraries 4-41 Configuring Model Libraries Though model libraries are usually configured for you, there are things that you sometimes must do manually.
4-42 Creating and Editing Models • Add Library* for global models.
Configuring Model Libraries 4-43 How PSpice A/D Uses Model Libraries PSpice A/D searches libraries for any information it needs to complete the definition of a part or to run a simulation. If an upto-date index does not already exist, PSpice A/D automatically generates an index file and uses the index to access only the model definitions relevant to the simulation.
4-44 Creating and Editing Models Adding Model Libraries to the Configuration Schematics always adds new libraries above the selected library name in the Library Files list box. To add model libraries to the configuration 1 From the Analysis menu, select Library and Include Files. 2 Click the library name positioned one entry below where you want to add the new library.
Configuring Model Libraries 4-45 Changing Local and Global Scope There are times when you might need to change the scope of a model library from local to global, or vice versa. To change the scope of a local model to global 1 From the Analysis menu, select Library and Include Files. 2 Select the model library that you want to change. 3 Click Add Library* to add a global entry. 4 Click Delete to remove the local entry.
4-46 Creating and Editing Models 2 Do not edit nom.lib. If you do, PSpice A/D will recreate the indexes for every model library referenced in nom.lib. This can take some time. If you have listed multiple .lib commands within a single library (like nom.lib), then edit the library using a text editor to change the order. Example: The model libraries diodes.lib and ediodes.lib (European manufactured diodes) shipped with your MicroSim programs have identically named device definitions.
Configuring Model Libraries 4-47 To change the library search path 1 In the schematic editor, from the Options menu, select Editor Configuration. 2 In the Library Path text box, position the pointer after the directory path that PSpice A/D should search before the new path. 3 Type in the new path name following these rules: • Use a semi-colon character ( ; ) to separate two path names. • Do not follow the last path name with a semi-colon.
Creating Symbols for Models 5 Chapter Overview This chapter provides information about creating symbols for model definitions so you can simulate the part from your schematic. Topics are grouped into four areas introduced later in this overview. If you want to find out quickly which tools to use to complete a given task and how to start, then: 1 Go to the roadmap in Ways to Create Symbols for Models on page 5-4. 2 Find the task you want to complete.
5-2 Creating Symbols for Models Background information These topics provide background on the things you need to know and do to prepare for creating symbols. • What’s Different About Symbols Used for Simulation? on page 5-3 • Preparing Your Models for Symbol Creation on page 5-5 Task roadmap This topic helps you find the sections in this chapter that are relevant to the symbol creation task that you want to complete.
What’s Different About Symbols Used for Simulation? 5-3 What’s Different About Symbols Used for Simulation? A symbol used for simulation has these special properties: • a link to a simulation model • a netlist translation • modeled pins • other simulation properties specific to the part, which can include hidden pin connections or propagation delay level (for digital parts) For information on adding simulation models to a model library, see Chapter 4,Creating and Editing Models.
5-4 Creating Symbols for Models Ways to Create Symbols for Models If you want to... Then do this... To find out more, see this... ➥ Automatically create Run the symbol wizard to create symbols from a model library. Using the Symbol Wizard on page 5-6 Basing New Symbols On a Custom Set of Symbols on page 5-13 Create AKO symbols using the symbol editor. Creating AKO Symbols on page 5-8 Run the Parts utility* and enable automatic creation of symbols.
Preparing Your Models for Symbol Creation 5-5 Preparing Your Models for Symbol Creation If you already have model definitions and want to create symbols for them, you should organize the definitions into libraries containing similar device types. To set up a model library for symbol creation 1 2 If all of your models are in one file and you wish to keep them that way, rename the file to: • reflect the kinds of models contained in the file, and • have the .lib extension.
5-6 Creating Symbols for Models Using the Symbol Wizard If: • you want to automatically create symbols for a set of similar model definitions that are saved in a model library, and • you do not need to minimize the size of the new symbol library to save disk space, then use the symbol wizard. How to Start the Symbol Wizard To start the symbol wizard for a set of model definitions in a library Start the symbol editor 1 In the schematic editor, from the File menu, select Edit Library.
Using the Symbol Wizard 5-7 How the Symbol Wizard Works The symbol wizard operates in four phases: setup, automatic symbol creation, refinement, and global configuration. Phase 1: Setup To begin, the symbol wizard asks you for: • the name of the model library that contains the model definitions, and • the name of the symbol library to save the new symbol definitions to. Phase 2: Automatic symbol creation Instead of using the MicroSim default symbol set, you can use your own set of standard symbols.
5-8 Creating Symbols for Models Phase 4, Global library configuration When you click Finish, the wizard saves the symbols to the symbol library you named in the setup phase and does the following: • Configures the symbol library for global use. • If the model library is not yet configured, configures it for global use. Creating AKO Symbols If you want to create a compact symbol library for a set of similar models, then create AKO symbols.
Creating AKO Symbols Note An AKO symbol can only reference base symbols contained in its own library. How to Create AKO Symbols AKO symbol creation is a two step process as follows: 1 Create the base symbol. 2 Add one or more AKO symbols. The following procedure explains how to create a new library with the base and AKO symbols. To create a new library with a base symbol and AKO symbols Start the symbol editor 1 From the File menu in the schematic editor, select Edit Library.
5-10 Creating Symbols for Models 3 Save the base symbol to a new library: a From the File menu, select Save As. b Type the name of the new library without the .slb extension. Make sure the new library name: c 4 • matches the name of the model library with the corresponding definitions, and • does not duplicate an existing library name. Click OK. Click YES when you are prompted to add this library to the list of Schematics' configured libraries.
Using the Parts Utility to Create Symbols 5-11 Completing the Configuration of Your Part The only thing left to do is to make sure PSpice A/D knows where to find the model library that contains the model definitions corresponding to the symbols you just created. To configure the model library 1 Click in the schematic editor window. 1 From the Analysis menu, select Library and Include Files. 2 In the File Name text box, type the name of the library including the file extension.
5-12 Creating Symbols for Models Starting the Parts Utility If you have already started the Parts utility from Schematics, and want to continue working on new models and symbols, then: To start the Parts utility alone 1 From the MicroSim program folder, select Parts. 2 From the File menu, select Open/Create, and enter an existing or new model library name. 3 From the Part menu, select New, Copy, or Import to load a device model. 1 Close the opened model library. 2 Open a new model library.
Basing New Symbols On a Custom Set of Symbols 5-13 Basing New Symbols On a Custom Set of Symbols If you are using the symbol wizard or the Parts utility to automatically generate symbols for model definitions, and you want to base the new symbols on a custom graphic standard (rather than the MicroSim default symbols), then you can change which underlying symbols either utility uses by setting up your own set of symbols.
5-14 Creating Symbols for Models *. Does not apply to the Parts utility. 2 For each custom symbol, set its MODEL attribute to `M where ` is a back-single quote or grave symbol. This tells the Parts utility or symbol wizard to substitute the correct model name.
Editing Symbol Graphics 5-15 Editing Symbol Graphics If you created symbols using the symbol wizard or the Parts utility, and you want to make further changes, the following sections explain a few key things to remember when you edit the symbols.
5-16 Creating Symbols for Models Defining Important Symbol Elements Origin The point of connection of a wire or pin is known as the hot-spot. The origin, denoted by a small box with a dashed outline, is the center point that the schematic editor uses when rotating a part instance. By convention, the origin of each symbol in the symbol library is placed at the point of connection to the upper far left pin on the device.
Editing Symbol Graphics 5-17 Grid spacing for graphics The grid, denoted by evenly spaced grid points, regulates the sizing and positioning of graphic objects and the positioning of pins. The default grid spacing is set at 0.1", and the minimum grid spacing is 0.01". You can change the grid spacing when you need to draw graphics in a tighter space. To change the grid spacing 1 From the Options menu in the symbol editor, select Display Options.
5-18 Creating Symbols for Models Here are the things to check when editing symbol attributes: ✔ Does the value of the MODEL attribute match the PSpice A/D .MODEL or .
Defining Symbol Attributes Needed for Simulation To find out more about this attribute... See this... MODEL page 5-19 SIMULATION ONLY page 5-19 TEMPLATE page 5-20 IO_LEVEL page 5-27 MNTYMXDLY page 5-28 IPIN(xxx) page 5-29 MODEL The MODEL attribute defines the name of the model that PSpice A/D must use for simulation. When defining this attribute, this rule applies: • The MODEL name should match the name of the .MODEL or .
5-20 Creating Symbols for Models When in the schematic editor, you cannot edit the TEMPLATE attribute. You must run the symbol editor to change this attribute. Creating symbols not destined for simulation TEMPLATE The TEMPLATE attribute defines the PSpice A/D syntax for the symbol’s netlist entry. When netlisting, the schematic editor substitutes actual values from the circuit into the appropriate places in the TEMPLATE syntax, then writes the translated statement to the netlist file.
Defining Symbol Attributes Needed for Simulation 5-21 Attribute names in templates Attribute names are preceded by a special character as follows: [ @ | ? | ~ | # | & ] The schematic editor processes the attribute according to the special character as shown in the following table. This syntax...* Is replaced with this... @ Value of . Error if no attribute or if no value assigned. & Value of if is defined. ?s...s Text between s...
5-22 Creating Symbols for Models Recommended scheme for netlist templates Templates for devices in the symbol library start with a PSpice A/D device letter, followed by the hierarchical path, and then the reference designator (REFDES) attribute. The ^ character in templates The schematic editor replaces the ^ character with the complete hierarchical path to the device being netlisted.
Defining Symbol Attributes Needed for Simulation TEMPLATE examples Simple resistor (R) template The R symbol has: • two pins: 1 and 2 • two required attributes: REFDES and VALUE Template R^@REFDES %1 %2 @VALUE Sample translation R_R23 abc def 1k where REFDES equals R23, VALUE equals 1k, and R is connected to nets abc and def.
5-24 Creating Symbols for Models Parameterized subcircuit call (X) template Suppose you have a subcircuit Z that has: • two pins: a and b • a subcircuit parameter: G, where G defaults to 1000 when no value is supplied To allow the parameter to be changed on the schematic, treat G as an attribute in the template. Note For clarity, the TEMPLATE attribute value is shown here in multiple lines; in a symbol definition, it is specified in one line (no line breaks).
Defining Symbol Attributes Needed for Simulation 5-25 Digital stimulus symbols with variable width pins template For a digital stimulus device template (such as that for a DIGSTIM symbol), a pin name can be preceded by a * character. This signifies the pin can be connected to a bus and the width of the pin is set equal to the width of the bus. Note For clarity, the TEMPLATE attribute value is shown here in multiple lines; in a symbol definition, it is specified in one line (no line breaks).
5-26 Creating Symbols for Models If the correspondence between pin names and nodes is as follows: This node name... Corresponds to this pin name... 10 IN+ 3 IN- 27 OUT+ 2 OUT- then the template would look like this: X^@REFDES %IN+ %IN- %OUT+ %OUT- @MODEL The rules of agreement are outlined in Figure 5-1.
Defining Symbol Attributes Needed for Simulation 5-27 IO_LEVEL The IO_LEVEL attribute defines what level of interface subcircuit model PSpice A/D must use for a digital part that is connected to an analog part. All digital symbols provided in the MicroSim libraries have an IO_LEVEL attribute. If you are creating a digital part, you need to To find out more about interface subcircuits, see Interface 1 Subcircuit Selection by PSpice A/D on page 15-3.
5-28 Creating Symbols for Models MNTYMXDLY All digital symbols provided in the MicroSim libraries have a MNTYMXDLY attribute. The MNTYMXDLY attribute defines the digital propagation delay level that PSpice A/D must use for a digital part. To find out more about propagation delays, see Timing Characteristics on page 7-11 and If you are creating a digital part, you need to do the following Selecting Propagation Delays on page 14-21.
Defining Symbol Attributes Needed for Simulation 5-29 IPIN attributes IPIN attributes define the net name to which a hidden (invisible) pin is connected. Whenever you define a hidden pin for a symbol, the symbol editor automatically creates an IPIN attribute. Hidden pins are typically used for power and ground on digital parts. The naming convention for IPIN attributes is IPIN(xxx) where xxx is the name of the pin.
Analog Behavioral Modeling 6 Chapter Overview This chapter describes how to use Analog Behavioral Modeling (ABM) feature provided in PSpice A/D. This chapter includes the following sections: Overview of Analog Behavioral Modeling on page 6-2 The abm.
6-2 Analog Behavioral Modeling Overview of Analog Behavioral Modeling The Analog Behavioral Modeling (ABM) feature provided in PSpice A/D allows for flexible descriptions of electronic components in terms of a transfer function or lookup table. In other words, a mathematical relationship is used to model a circuit segment so the segment need not be designed component by component.
The abm.slb Symbol Library File 6-3 The abm.slb Symbol Library File The symbol file abm.slb contains the ABM components. This file can logically be thought of as consisting of two sections. The first section contains symbols that can be quickly connected to form “control system” types of circuits. These components have names like SUM, GAIN, LAPLACE, and HIPASS. The second section contains symbols that are useful for more traditional “controlled source” forms of schematic parts.
6-4 Analog Behavioral Modeling Placing and Specifying ABM Parts ABM parts are placed and connected in the same way as other part symbols. Once an ABM symbol is placed, the instance attributes can be edited, effectively customizing the operational behavior of the part. This is equivalent to defining an ABM expression describing how inputs are transformed into outputs. The following sections discuss some of the rules for specifying ABM expressions.
Placing and Specifying ABM Parts resulting netlist. When a match is found, the original fragment is replaced by the fully qualified name of the net or device. For example, suppose we have a hierarchical part U1. Inside the schematic representing U1 we have an ABM expression including the term V(Reference). If “Reference” is the name of a local net, then the fragment written to the netlist will be translated to V(U1_Reference).
6-6 Analog Behavioral Modeling ABM Part Templates For most ABM symbols, a single PSpice A/D “E” or “G” device declaration is output to the netlist per symbol instance. The TEMPLATE attribute in these cases is straightforward. For example the LOG symbol defines an expression variant of the E device with its output being the natural logarithm of the voltage between the input pin and ground: E^@REFDES %out 0 VALUE { LOG(V(%in)) } The fragment E^@REFDES is standard.
Control System Parts Control System Parts Control system parts have single-pin inputs and outputs. The reference for input and output voltages is analog ground (0). An enhancement to PSpice A/D means these components can be connected together with no need for dummy load or input resistors. Table 6-1 lists the control system parts, grouped by function. Also listed are characteristic attributes that may be set. In the sections that follow, each part and its attributes are described in more detail.
6-8 Analog Behavioral Modeling Table 6-1 Control System Parts (continued) Category Symbol Description Laplace Transform LAPLACE Laplace expression NUM, DENOM Math Functions (where ‘x’ is the input) ABS |x| SQRT x1/2 PWR |x|EXP EXP PWRS xEXP EXP LOG ln(x) LOG10 log(x) EXP ex SIN sin(x) COS cos(x) TAN tan(x) ATAN tan-1 (x) ARCTAN tan-1 (x) ABM no inputs, V out EXP1...EXP4 ABM1 1 input, V out EXP1...EXP4 ABM2 2 inputs, V out EXP1...EXP4 ABM3 3 inputs, V out EXP1...
Control System Parts Basic Components The basic components provide fundamental functions and in many cases, do not require specifying attribute values. These parts are described below. CONST VALUE constant value The CONST part outputs the voltage specified by the VALUE attribute. This part provides no inputs and one output. SUM The SUM part evaluates the voltages of the two input sources, adds the two inputs together, then outputs the sum. This part provides two inputs and one output.
6-10 Analog Behavioral Modeling Limiters The Limiters can be used to restrict an output to values between a set of specified ranges. These parts are described below. LIMIT HI upper limit value LO lower limit value The LIMIT part constrains the output voltage to a value between an upper limit (set with the HI attribute) and a lower limit (set with the LO attribute). This part takes one input and provides one output.
Control System Parts 6-11 Chebyshev Filters The Chebyshev filters allow filtering of the signal based on a set of frequency characteristics. The output of a Chebyshev filter depends upon the analysis being done. For DC and bias point, the output is simply the DC response of the filter. For AC analysis, the output for each frequency is the filter response at that frequency. For transient analysis, the output is then the convolution of the past values of the input with the impulse response of the filter.
6-12 Analog Behavioral Modeling minimum stop band attenuation is 50 dB. Assuming that the input to the filter is the voltage at net 10 and output is a voltage between nets 5 and 0, this will produce a PSpice A/D netlist declaration like this: ELOWPASS 5 0 CHEBYSHEV {V(10)} = LP 800 1.2K .
Control System Parts 6-13 band ripple is 0.1 dB and the minimum stop band attenuation is 50 dB. This will produce a PSpice A/D netlist declaration like this: EBANDPASS 5 0 CHEBYSHEV + {V(10)} = BP 800 1.2K 2K 3K .1dB 50dB BANDREJ RIPPLE is the pass band ripple in dB STOP is the stop band attenuation in dB F0, F1, F2, F3 are the cutoff frequencies The BANDREJ part is characterized by four cutoff frequencies.
6-14 Analog Behavioral Modeling Integrator and Differentiator The integrator and differentiator parts are described below. INTEG IC initial condition of the integrator output GAIN gain value The INTEG part implements a simple integrator. A current source/capacitor implementation is used to provide support for setting the initial condition. DIFFER GAIN gain value The DIFFER part implements a simple differentiator. A voltage source/capacitor implementation is used.
Control System Parts 6-15 FTABLE ROWn either an (input frequency, magnitude, phase) triplet, or an (input frequency, real part, imaginary part) triplet describing a complex value; by default, up to five triplets are allowed where n=1, 2, 3, 4, or 5 DELAY group delay increment; defaults to 0 if left blank R_I table type; if left blank, the frequency table is interpreted in the (input frequency, magnitude, phase) format; if defined with any value (such as YES), the table is interpreted in the (input fr
6-16 Analog Behavioral Modeling GVALUE parts, Modeling Mathematical or Instantaneous Relationships on page 6-30). The output for each frequency is then the input times the gain, times the value of the table at that frequency. For transient analysis, the voltage is evaluated at each time point. The output is then the convolution of the past values with the impulse response of the frequency response. These rules follow the standard method of using Fourier transforms.
Control System Parts This part is characterized by the following attributes: ROW1 = 0Hz ROW2 = 5kHz ROW3 = 6kHz DELAY = R_I = MAGUNITS = PHASEUNITS = 0 0 -60 0 -5760 -6912 Since R_I, MAGUNITS, and PHASEUNITS are undefined, each table entry is interpreted as containing frequency, magnitude value in dB, and phase values in degrees. Delay defaults to 0.
6-18 Analog Behavioral Modeling Laplace Transform Part The LAPLACE part specifies a Laplace transform which is used to determine an output for each input value. LAPLACE NUM numerator of the Laplace expression DENOM denominator of the Laplace expression The LAPLACE part uses a Laplace transform description. The input to the transform is a voltage. The numerator and denominator of the Laplace transform function are specified as attributes for the symbol.
Control System Parts 6-19 gain has both a real and an imaginary component. For transient analysis, the output is the convolution of the input waveform with the impulse response of 1/(1+.001·s). The impulse response is a decaying exponential with a time constant of 1 millisecond. This means that the output is the “lossy integral” of the input, where the loss has a time constant of 1 millisecond. The LAPLACE part shown in Figure 6-6 could be used for this purpose.
6-20 Analog Behavioral Modeling If R is small, the characteristic impedance of such a line is Z = ((R + j·ω·L)/(j·ω·C))1/2, the delay per unit length is (L C)1/ 2, and the loss in dB per unit length is 23·R/Z. This could be represented by the device in Figure 6-8. The parameters R, L, and C can be defined in a .PARAM statement contained in a model file. (Refer to the online MicroSim PSpice A/D Reference Manual for more information about using .PARAM statements.
Control System Parts Math Functions The ABM math function parts are shown in Table 6-2. For each device, the corresponding template is shown, indicating the order in which the inputs are processed, if applicable. Table 6-2 ABM Math Function Parts For this device... Output is the...
6-22 Analog Behavioral Modeling requirements. Each of these parts has a set of four expression building block attributes of the form: EXPn where n = 1, 2, 3, or 4. During netlist generation, the complete expression is formed by concatenating the building block expressions in numeric order, thus defining the transfer function. Hence, the first expression fragment should be assigned to the EXP1 attribute, the second fragment to EXP2, and so on.
Control System Parts 6-23 In this example of an ABM device, the output voltage is set to 5 volts times the square root of the voltage between net 3 and net 2. The attribute settings for this part are as follows: EXP1 = 5V * EXP2 = SQRT(V(%IN2,%IN1)) This will produce a PSpice A/D netlist declaration like this: ESQROOT 4 0 VALUE = {5V*SQRT(V(3,2))} Example 2 GPSK is an oscillator for a PSK (Phase Shift Keyed) modulator. Current is pumped from net 11 through the source to net 6.
6-24 Analog Behavioral Modeling Example 3 Figure 6-11 ABM Expression Part Example 3 A device, EPWR, computes the instantaneous power by multiplying the voltage across nets 5 and 4 by the current through VSENSE. Sources are controlled by expressions which may contain voltages or currents or both. The ABM2 part (two inputs, current output) in Figure 6-11 could represent this.
Control System Parts An Instantaneous Device Example: Modeling a Triode This section provides an example of using various ABM parts to model a triode vacuum tube. The schematic of the triode subcircuit is shown in Figure 6-13. Figure 6-13 Triode Circuit Assumptions: In its main operating region, the triode’s current is proportional to the 3/2 power of a linear combination of the grid and anode voltages: ianode = k0*(vg + k1*va)1.5 For a typical triode, k0 = 200e-6 and k1 = 0.12.
6-26 Analog Behavioral Modeling EXP1 = V(%IN2,%IN3)+ EXP2 = 0.12*V(%IN1,%IN3) This works for the main operating region but does not model the case in which the current stays 0 when combined grid and anode voltages go negative. We can accommodate that situation as follows by adding the LIMIT part with the following characteristics: HI = 1E3 LO = 0 This part instance, LIMIT1, converts all negative values of vg+.12*va to 0 and leaves all positive values (up to 1 kV) alone.
Control System Parts impedance. Capacitances between the grid, cathode, and anode are also needed. The lower part of the schematic in Figure 6-13 shows a possible method for incorporating these effects. To complete the example, one could add a circuit which produces the family of I-V curves (shown in Figure 6-14).
6-28 Analog Behavioral Modeling PSpice A/D-Equivalent Parts PSpice A/D-equivalent parts respond to a differential input and have double-ended output. These parts reflect the structure of PSpice A/D “E” and “G” devices, thus having two pins for each controlling input and the output in the symbol. Table 6-4 summarizes the PSpice A/D-equivalent parts available in the symbol library.
PSpice A/D-Equivalent Parts voltage output is required, use an E part type. If a current output is necessary, use a G part type. Each E or G part type in the abm.slb symbol file is defined by a template that provides the specifics of the transfer function. Other attributes in the model definition can be edited to customize the transfer function. By default, the template cannot be modified directly using Attributes on the Edit menu in Schematics.
6-30 Analog Behavioral Modeling specifies the form of the transfer function to be used, as one of: VALUE TABLE LAPLACE FREQ CHEBYSHEV arithmetic expression lookup table Laplace transform frequency response table Chebyshev filter characteristics specifies the transfer function as a formula or lookup table as required by the specified Refer to the online MicroSim PSpice A/D Reference Manual for detailed information.
PSpice A/D-Equivalent Parts 6-31 be either the voltage at a net, such as V(5), or the voltage across two nets, such as V(4,5). Currents must be the current through a voltage source (V device), for example, I(VSENSE). Voltage sources with a value of 0 are handy for sensing current for use in these expressions. Functions may be used in expressions, along with arithmetic operators (+, -, *, and /) and parentheses. Available built-in functions are summarized in Table 3-2 on page 3-18.
6-32 Analog Behavioral Modeling EMULT, GMULT, ESUM, and GSUM The EMULT and GMULT parts provide output which is based on the product of two input sources. The ESUM and GSUM parts provide output which is based on the sum of two input sources. The complete transfer function may also include other mathematical expressions. Example 1 Consider the device in Figure 6-17. This device computes the instantaneous power by multiplying the voltage across pins %IN+ and %IN- by the current through VSENSE.
PSpice A/D-Equivalent Parts where MAXREAL is a PSpice A/D internal constant representing a very large number (on the order of 1e30). In general, the result of evaluating an expression is limited to MAXREAL. Note that the output of the symbol can also be used as part of the controlling function. To create this device, you would first make a new symbol, GDIV, based on the GMULT part. Edit the GDIV template to divide the two input values rather than multiply them.
6-34 Analog Behavioral Modeling TABLE = + (0, 0) (.02, 2.690E-03) (.04, 4.102E-03) (.06, 4.621E-03) + (.08, 4.460E-03) (.10, 3.860E-03) (.12, 3.079E-03) (.14, + 2.327E-03) + (.16, 1.726E-03) (.18, 1.308E-03) (.20, 1.042E-03) (.22, + 8.734E-04) + (.24, 7.544E-04) (.26, 6.566E-04) (.28, 5.718E-04) (.30, + 5.013E-04) + (.32, 4.464E-04) (.34, 4.053E-04) (.36, 3.781E-04) (.38, + 3.744E-04) + (.40, 4.127E-04) (.42, 5.053E-04) (.44, 6.380E-04) (.46, + 7.935E-04) + (.48, 1.139E-03) (.50, 2.605E-03) (.52, 8.
PSpice A/D-Equivalent Parts 6-35 Frequency-Domain Device Models Frequency-domain models (ELAPLACE, GLAPLACE, EFREQ, and GFREQ) are characterized by output that depends on the current input as well as the input history. The relationship is therefore non-instantaneous. For example, the output may be equal to the integral of the input over time. In other words, the response depends upon frequency. During AC analysis, the frequency response determines the complex gain at each frequency.
6-36 Analog Behavioral Modeling frequency gain times the value of EXPR. The zero frequency gain is the value of XFORM with s = 0. For AC analysis, EXPR is linearized around the bias point (similar to the VALUE parts). The output is then the input times the gain of EXPR times the value of XFORM. The value of XFORM at a frequency is calculated by substituting j·w for s, where w is 2p·frequency. For transient analysis, the value of EXPR is evaluated at each time point.
PSpice A/D-Equivalent Parts gain has both a real and an imaginary component. The gain and phase characteristic is the same as that shown for the equivalent control system part example using the LAPLACE part (see Figure 6-7 on page 6-19). For transient analysis, the output is the convolution of the input waveform with the impulse response of 1/(1+.001·s). The impulse response is a decaying exponential with a time constant of 1 millisecond.
6-38 Analog Behavioral Modeling R_I table type; if left blank, the frequency table is interpreted in the (input frequency, magnitude, phase) format; if defined with any value (such as YES), the table is interpreted in the (input frequency, real part, imaginary part) format. MAGUNITS units for magnitude where the value can be DB (decibels) or MAG (raw magnitude); defaults to DB if left blank.
PSpice A/D-Equivalent Parts .001 (-60 dB) for frequencies above 6 kilohertz. The output is a voltage across the output pins. This part is defined by the following attributes: TABLE = (0, 0, 0) (5kHz, 0, -5760) (6kHz, -60, -6912) DELAY = R_I = MAGUNITS = PHASEUNITS = Since R_I, MAGUNITS, and PHASEUNITS are undefined, each table entry is interpreted as containing frequency, magnitude value in dB, and phase values in degrees. Delay defaults to 0.
6-40 Analog Behavioral Modeling Cautions and Recommendations for Simulation and Analysis Instantaneous Device Modeling During AC analysis, nonlinear transfer functions are handled the same way as other nonlinear parts: each function is linearized around the bias point and the resulting small-signal equivalent is used. Consider the voltage multiplier (mixer) shown in Figure 6-20. This circuit has the following characteristics: Vin1: Vin2: DC=0v AC=1v DC=0v AC=1v where the output on net 3 is V(1)*V(2).
Cautions and Recommendations for Simulation and Analysis Frequency-Domain Parts Some caution is in order when moving between frequency and time domains. This section discusses several points that are involved in the implementation of frequency-domain parts. These discussions all involve the transient analysis, since both the DC and AC analyses are straightforward. The first point is that there are limits on the maximum values and on the resolution of both time and frequency.
6-42 Analog Behavioral Modeling (2π) = 159 Hz. At 159 Hz, the response is down to .001 (down by 60 db). Since some transforms do not have such a limit, there is also a limit of 10/RELTOL times the frequency resolution, or 10/(RELTOL·TSTOP). For example, consider the transform: e-0.001·s This is an ideal delay of 1 millisecond and has no frequency cutoff. If TSTOP = 10 milliseconds and RELTOL=.001, then PSpice A/D imposes a frequency cutoff of 10 MHz.
Cautions and Recommendations for Simulation and Analysis A good example of this is the expression {S}, which corresponds to differentiation in the time domain. The impulse response for {S} is an impulse pair separated by an infinitesimal distance in time. The impulses have opposite signs, and are situated one in the infinitesimal past, the other in the infinitesimal future. In other words, convolution with this corresponds to applying a finite-divided difference in the time domain.
6-44 Analog Behavioral Modeling TMAX is not specified it is assigned a value, or if it is specified, it may be reduced. For low pass and band pass filters, TMAX is set to (0.5/FS), where FS is the stop band cutoff in the case of a low pass filter, or the upper stop band cutoff in the case of a band pass filter. For high pass and band reject filters, there is no clear way to apply the Nyquist criterion directly, so an additional factor of two is thrown in as a safety margin. Thus, TMAX is set to (0.
Cautions and Recommendations for Simulation and Analysis Trading Off Computer Resources For Accuracy It should be clear from the foregoing discussion that there is a significant trade-off between accuracy and computation time for parts modeled in the frequency domain. The amount of computer time and memory scale approximately inversely to RELTOL. Therefore, if you can use RELTOL=.01 instead of the default .001, you will be ahead.
6-46 Analog Behavioral Modeling Basic Controlled Sources As with basic SPICE, PSpice A/D has basic controlled sources derived from the standard SPICE E, F, G, and H devices. Table 6-5 summarizes the linear controlled source types provided in the standard symbol library. Table 6-5 Basic Controlled Sources in analog.
Digital Device Modeling 7 Chapter Overview This chapter provides information about digital modeling, and includes the following sections: Introduction on page 7-2 Functional Behavior on page 7-3 Timing Characteristics on page 7-11 Input/Output Characteristics on page 7-17
7-2 Digital Device Modeling Introduction The standard symbol libraries contain a comprehensive set of digital parts in many different technologies. Each digital part is described electrically by a digital device model in the form of a subcircuit definition stored in a model library. The corresponding subcircuit name is defined by the part’s MODEL attribute value.
Functional Behavior Functional Behavior A digital device model’s functional behavior is defined by one or more interconnected digital primitives. Typically, a logic diagram in a data book can be implemented directly using the primitives provided by PSpice A/D. Table 7-1 provides a summary of the digital primitives.
7-4 Digital Device Modeling Table 7-1 Digital Primitives Summary (continued) Type Description Tristate Gates BUF3 buffer INV3 inverter AND3 AND gate NAND3 NAND gate OR3 OR gate NOR3 NOR gate XOR3 exclusive OR gate NXOR3 exclusive NOR gate BUF3A buffer array INV3A inverter array AND3A AND gate array NAND3A NAND gate array OR3A OR gate array NOR3A NOR gate array XOR3A exclusive OR gate array NXOR3A exclusive NOR gate array Bidirectional Transfer Gates NBTG N-channel transf
Functional Behavior Table 7-1 Digital Primitives Summary (continued) Type Description Programmable Logic Arrays PLAND AND array PLOR OR array PLXOR exclusive OR array PLNAND NAND array PLNOR NOR array PLNXOR exclusive NOR array PLANDC AND array, true and complement PLORC OR array, true and complement PLXORC exclusive OR array, true and complement PLNANDC NAND array, true and complement PLNORC NOR array, true and complement PLNXORC exclusive NOR array, true and complement Memory
7-6 Digital Device Modeling The format for digital primitives is similar to that for analog devices. One difference is that most digital primitives require two models instead of one: • The Timing Model, which specifies propagation delays and timing constraints such as setup and hold times. • The I/O Model, which specifies information specific to the device’s input/output characteristics.
Functional Behavior Digital Device .subckt 7400 A B Y + params: MNTYMXDLY=0 IO_LEVEL=0 + optional: DPWR=$G_DPWR DGND=$G_DGND U1 NAND(2) DPWR DGND A B Y IO_STD + D_7400 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} Timing Model I/O Model .model IO_STD uio ( + drvh=96.4 drvl=104 + AtoD1="AtoD_STD" AtoD2="AtoD_STD_NX" + AtoD3="AtoD_STD" AtoD4="AtoD_STD_NX" + DtoA1="DtoA_STD" DtoA2="DtoA_STD" + DtoA3="DtoA_STD" DtoA4="DtoA_STD" + tswhl1=1.373ns tswlh1=3.382ns ... + DIGPOWER="DIGIFPWR" ) .
7-8 Digital Device Modeling are the nodes used by the interface subcircuits which connect analog nodes to digital nodes or vice versa. * is one or more input and output nodes. The number of nodes depends on the primitive type and its parameters. Analog devices, digital devices, or both may be connected to a node.
Functional Behavior IO_LEVEL is an optional device parameter which selects one of the four AtoD or DtoA interface subcircuits from the device’s I/O Model. PSpice A/D calls the selected subcircuit automatically in the event a node connecting to the primitive also connects to an analog device. If not specified, IO_LEVEL defaults to 0.
7-10 Digital Device Modeling + MNTYMXDLY={MNTYMXDLY} U3 jkff(1) DPWR DGND + $D_HI CLRBAR QB_BUF $D_HI $D_HI + QC_BUF $D_NC D_393_2 IO_STD + MNTYMXDLY={MNTYMXDLY} U4 jkff(1) DPWR DGND + $D_HI CLRBAR QC_BUF $D_HI $D_HI + QD_BUF $D_NC D_393_3 IO_STD + MNTYMXDLY={MNTYMXDLY} UBUFF bufa(4) DPWR DGND + QA_BUF QB_BUF QC_BUF QD_BUF + QA QB QC QD D_393_4 IO_STD + MNTYMXDLY={MNTYMXDLY} + IO_LEVEL={IO_LEVEL} .
Timing Characteristics 7-11 Timing Characteristics A digital device model’s timing behavior can be defined in one of two ways: • Most primitives have an associated Timing Model, in which propagation delays and timing constraints (such as setup/ hold times) are specified. This method is used when it is easy to partition delays among individual primitives; typically when the number of primitives is small.
7-12 Digital Device Modeling typical low-to-high propagation delay on a gate is specified as the parameter TPLHTY. The minimum data-to-clock setup time on a flip-flop is specified as the parameter TSUDCLKMN. Several timing models are used by digital device 74393 from the model libraries. One of them, D_393_1, is shown below for an edge-triggered flip-flop. .
Timing Characteristics DIGMNTYSCALE This option computes the minimum delay when a typical delay is known, using the formula: TPxxMN = DIGMNTYSCALE ⋅ TPxxTY DIGMNTYSCALE defaults to the value 0.4, or 40% of the typical delay. Its value must be between 0.0 and 1.0. DIGTYMXSCALE This option computes the maximum delay from a typical delay, using the formula TPxxMX = DIGTYMXSCALE ⋅ TPxxTY DIGTYMXSCALE defaults to the value 1.6. Its value must be greater than 1.0.
7-14 Digital Device Modeling Instead, when one or more timing constraints are omitted, the simulator uses the following steps to fill in the missing values: • If the minimum value is omitted, it defaults to zero. • If the maximum value is omitted, it takes on the typical value if one was specified, otherwise it takes on the minimum value. • If the typical value is omitted, it is computed as the average of the minimum and maximum values.
Timing Characteristics When outputs connect to analog devices, the propagation delay is reduced by the switching times specified in the I/O Model. 7-15 See Input/Output Characteristics on page 7-17 for more information. Inertial and Transport Delay The simulator uses two different types of internal delay functions when simulating the digital portion of the circuit: inertial delay and transport delay.
7-16 Digital Device Modeling 20 40 30 50 TPLHTY=10 TPHLTY=10 (TPWRT not set) The same device with a short pulse applied produces no output change. 20 22 TPLHTY=10 TPHLTY=10 (TPWRT not set) However, if TPWRT is assigned a numerical value (1 or 2 for this example), then the device outputs a glitch.
Input/Output Characteristics Input/Output Characteristics A digital device model’s input/output characteristics are defined by the I/O Model that it references. Some characteristics, such as output drive resistance and loading capacitances, apply to digital simulation. Others, such as the interface subcircuits and the power supplies, apply only to mixed analog/digital simulation.
7-18 Digital Device Modeling INLD and OUTLD These are used in the calculation of loading capacitance, which factors into the propagation delay discussed under Timing Models on Timing Model on page 7-11. Note that INLD does not apply to stimulus generators because they have no input nodes. DRVH and DRVL These are used to determine the strength of the output. Strengths are discussed on Defining Output Strengths on page 7-21.
Input/Output Characteristics 7-19 TSWLHn and TSWHLn These switching times are subtracted from a device’s propagation delay on the outputs which connect to interface nodes. This compensates for the time it takes the DtoA device to change its output voltage from its current level to that of the switching threshold. By subtracting the switching time from the propagation delay, the analog signal reaches the switching threshold at the correct time (that is, at the exact time of the digital transition).
7-20 Digital Device Modeling Table 7-2 Digital I/O Model Parameters (continued) UIO Model Parameters Description AtoD1 (Level 1) name of AtoD interface subcircuit DtoA1 (Level 1) name of DtoA interface subcircuit AtoD2 (Level 2) name of AtoD interface subcircuit DtoA2 (Level 2) name of DtoA interface subcircuit AtoD3 (Level 3) name of AtoD interface subcircuit DtoA3 (Level 3) name of DtoA interface subcircuit AtoD4 (Level 4) name of AtoD interface subcircuit DtoA4 (Level 4) name of DtoA i
Input/Output Characteristics 7-21 The digital primitives comprising the 74393 part, reference the IO_STD I/O Model in the model libraries as shown: .model IO_STD uio ( + drvh=96.4 drvl=104 + AtoD1="AtoD_STD" AtoD2="AtoD_STD_NX" + AtoD3="AtoD_STD" AtoD4="AtoD_STD_NX" + DtoA1="DtoA_STD" DtoA2="DtoA_STD" + DtoA3="DtoA_STD" DtoA4="DtoA_STD" + tswhl1=1.373ns tswlh1=3.382ns + tswhl2=1.346ns tswlh2=3.424ns + tswhl3=1.511ns tswlh3=3.517ns + tswhl4=1.487ns tswlh4=3.
7-22 Digital Device Modeling Configuring the strength scale You can set these options by selecting Setup from the Analysis menu in Schematics. The 64 strengths are determined by two configurable options: DIGDRVZ and DIGDRVF. DIGDRVZ defines the impedance of the Z strength, and DIGDRVF defines the impedance of the forcing strength. These two values define a logarithmic scale consisting of 64 ranges of impedance values. By default, DIGDRVZ is 20 kohms and DIGDRVF is 2 ohms.
Input/Output Characteristics 7-23 level is at a higher strength than the 1 level (which drives at the Z strength). Drive impedances which are higher than the value of DIGDRVZ are assigned the Z strength (0). Likewise, drive impedances lower than the value of DIGDRVF are assigned the forcing strength (63). Controlling overdrive During a simulation, the simulator uses only the strength range number (0-63) to compare the driving strength of outputs.
7-24 Digital Device Modeling and output leakage currents would be required, as well as low coupling from adjacent signals. The simulator models the stored charge nets using a simplified switch-level simulation technique. A normalized (with respect to power supply) charge or discharge current is calculated for each output or transfer gate attached to the net. This current, divided by the net’s total capacitance, is integrated and recalculated at intervals which are appropriate for the particular net.
Input/Output Characteristics Creating Your Own Interface Subcircuits for Additional Technologies If you are creating custom digital parts for a technology which is not in the model libraries, you may also need to create AtoD and DtoA subcircuits. The new subcircuits need to be referenced by the I/O Models for that technology. The AtoD and DtoA interfaces have specific formats, such as node order and parameters, which are expected by PSpice A/D for mixed-signal simulations.
7-26 Digital Device Modeling The DtoA interface subcircuit format is shown here: .SUBCKT DTOA + + + PARAMS: DRVL=<0 level driving resistance> + DRVH=<1 level driving resistance> + CAPACITANCE=
Input/Output Characteristics 7-27 If an instance of the 74393 part is connected to an analog part via node AD_NODE, PSpice A/D generates an interface block using the I/O Model specified by the digital primitive actually at the interface. Suppose that U1 is the primitive connected at AD_NODE (see the 74393 subcircuit definition on page 9), and that the IO_LEVEL is set to 1. PSpice A/D determines that IO_STD is the I/O Model used by U1.
7-28 Digital Device Modeling .subckt DtoA_STD D A DPWR DGND + params: DRVL=0 DRVH=0 CAPACITANCE=0 * N1 A DGND DPWR DIN74 DGTLNET=D IO_STD C1 A DGND {CAPACITANCE+0.1pF} .ends For this subcircuit, the DRVH and DRVL parameters values specified in the IO_STD model would be passed to it. (The interface subcircuits in the model libraries do not currently use these values.) The DtoA_STD interface subcircuit references the DIN74 model in its PSpice A/D N device declaration.
Creating a Digital Model Using the PINDLY and LOGICEXP Primitives Creating a Digital Model Using the PINDLY and LOGICEXP Primitives Unlike the majority of analog device types, the bulk of digital devices are not primitives that are compiled into the simulator. Instead, most digital models are macro models or subcircuits that are built from a few primitive devices.
7-30 Digital Device Modeling hold timing from the data sheet. Then the simulator can verify that these conditions are met during the simulation. Digital Primitives Primitives in the simulator are devices or functions which are compiled directly into the code. The primitives serve as fundamental building blocks for more complex macro models. There are two types of primitives in the simulator: gate level and behavioral.
Creating a Digital Model Using the PINDLY and LOGICEXP Primitives name, interface pin list, and parameter list is the LOGICEXP primitive. It contains everything in the component that can be expressed in terms of simple combinational logic. The logic expression device also serves to buffer other input signals that will go to the PINDLY primitive. In this case, LOGICEXP buffers the ENP_I, ENT_I, CLK_I, CLRBAR_I, LOADBAR_I, and four data signals.
7-32 Digital Device Modeling primitives, see the Digital Devices chapter in the online MicroSim PSpice A/D Reference Manual. IO_STD, shown in the listing, is the standard I/O model. This determines the A-to-D and D-to-A interface characteristics for the subcircuit. The device contains family-specific information, but the models have been created for nearly all of the stock families. The various I/O models can be found in the library file dig_io.lib. The logic expressions themselves are straightforward.
Creating a Digital Model Using the PINDLY and LOGICEXP Primitives Pin-to-Pin Delay (PINDLY Primitive) The delay and constraint specifications for the model are specified using the PINDLY primitive. The PINDLY primitive is evaluated every time any of its inputs or outputs change. See the Digital Devices chapter in the online MicroSim PSpice A/D Reference Manual for more information. For the 74160, we have five delay paths, the four flip-flop outputs to subcircuit outputs QA...QD to QA_O...
7-34 Digital Device Modeling In the 74160 model, the boolean expressions are actually reference functions. There are three reference functions available: CHANGED, CHANGED_LH, and CHANGED_HL. The format is: function name (node, delta time) For our example, we define the variable CLOCK as a logical TRUE if there has been a LO-to-HI transition of the CLK signal at simulation time. We define CNTENT as TRUE if there has been any transition of the ENT signal at the simulation time.
Creating a Digital Model Using the PINDLY and LOGICEXP Primitives delay in every CASE function. Also note that the expressions must be separated by a comma. In the PINDLY section of the PINDLY primitive in the model listing, the four output nodes (QA_O through QD_O) all use the same delay rules. The CASE function is evaluated independently for each of the outputs in turn.
7-36 Digital Device Modeling Constraint Checker (CONSTRAINT Primitive) The CONSTRAINT primitive provides a general constraint checking mechanism to the digital device modeler. It performs setup and hold time checks, pulse width checks, frequency checks, and includes a general mechanism to allow user-defined conditions to be reported. See the Digital Devices chapter in the online MicroSim PSpice A/D Reference Manual for more information.
Creating a Digital Model Using the PINDLY and LOGICEXP Primitives signal can go inactive before the active clock edge. Again, the _LH and _HL forms are available. The difference between RELEASETIME and SETUPTIME checking is that simultaneous CLOCK/DATA transitions are never allowed (this assumes a nonzero hold time). RELEASETIME is usually not used in conjunction with SETUPTIME or HOLDTIME. Width WIDTH does the minimum pulse-width checking.
7-38 Digital Device Modeling B, C, D) have a setup/hold time of 20 ns in reference to the CLK signal. We are also checking that ENP and ENT have a setup/ hold time of 20 ns with respect to the 0 to 1 transition of the CLK signal, but only when the conditions in the WHEN statement are met. All of the delay and constraint checking values were taken directly from the actual data sheet. This makes the delay modeling both easy and accurate.
Creating a Digital Model Using the PINDLY and LOGICEXP Primitives + I1C = { (QA & EN & QB) | LOAD } + I2C = { ~(LOAD & C) } + JC = { I1C & ~(LOAD & I2C) } + KC = { I1C & I2C } + I1D = { ((QC & QB & QA & EN) | (EN & QA & QD)) | LOAD } + I2D = { ~(LOAD & D) } + JD = { I1D & ~(LOAD & I2D) } + KD = { I1D & I2D } + RCO = { QD & QA & ENT } * UJKFF JKFF(4) DPWR DGND $D_HI CLRBAR CLKBAR JA JB JC JD KA KB KC KD + QA QB QC QD QABAR QBBAR QCBAR QDBAR D0_EFF IO_STD U160DLY PINDLY (5,0,10) DPWR DGND + RCO QA QB QC QD +
7-40 Digital Device Modeling + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { CLRBAR!='0 & (LOADBAR!='0 ^ + CHANGED(LOADBAR,0)) + & CHANGED(EN,20NS) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 25NS + WHEN = { CLRBAR!='0 } + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 20NS .
Part Three Setting Up and Running Analyses Part Three describes how to set up and run analyses and provides setup information specific to each analysis type. Chapter 8,Setting Up Analyses and Starting Simulation, explains the procedures general to all analysis types to set up and start the simulation. Chapter 9,DC Analyses, describes how to set up DC analyses, including DC sweep, bias point detail, small-signal DC transfer, and DC sensitivity.
Chapter 13,Monte Carlo and Sensitivity/Worst-Case Analyses, describes how to set up Monte Carlo and sensitivity/worst-case analyses for statistical interpretation of your circuit’s behavior. Chapter 14,Digital Simulation, describes how to set up a digital simulation analysis on either a digital-only or mixed-signal circuit. Chapter 15,Mixed Analog/Digital Simulation, explains how PSpice A/D processes the analog and digital interfaces in mixed-signal circuits.
Setting Up Analyses and Starting Simulation 8 Chapter Overview This chapter provides an overview of setting up analyses and starting simulation which applies to any analysis type. The other chapters in Part Three, Setting Up and Running Analyses provide specific analysis setup information for each analysis type.
8-2 Setting Up Analyses and Starting Simulation Analysis Types PSpice A/D supports analyses that can simulate analog-only, mixed-signal, and digital-only circuits. PSpice A/D fully supports digital analysis by simulating the timing behavior of digital devices within a standard transient analysis, including worst-case (min/max) timing. For mixed analog/digital circuits, all of the above-mentioned analyses can be run. If the circuit is digital-only, only the transient analysis can be run.
Setting Up Analyses Table 8-1 8-3 Classes of PSpice A/D Analyses (continued) Analysis Analysis Setup Dialog Box Swept Variable Statistical analyses Monte Carlo Monte Carlo/ worst-case Sensitivity/worst-case Monte Carlo/ worst-case The Probe waveform analyzer is used to display and graphically analyze the results of PSpice A/D simulations for swept analyses. Supplementary analysis information is generated to the simulation output file in the form of lists and tables.
8-4 Setting Up Analyses and Starting Simulation Execution Order for Standard Analyses During simulation, any analyses that are enabled are performed in the order shown in Table 8-2. Each type of analysis is conducted at most once per run. Several of the analyses (small-signal transfer, DC sensitivity, and frequency response) depend upon the bias point calculation. Since so many analyses use the bias point, PSpice A/D calculates it automatically.
Setting Up Analyses Output Variables Certain analyses (such as noise, Monte Carlo, sensitivity/worstcase, DC sensitivity, Fourier, and small-signal DC transfer function) require you to specify output variables for voltages and currents at specific points on the schematic.
8-6 Setting Up Analyses and Starting Simulation A (from line 4) is uniquely distinguished by specifying the full part name (as described above) followed by a colon, and the pin name. For example, the pins on a capacitor with reference designator C31 placed on a top-level page and pin names 1 and 2 would be identified as C31:1 and C31:2, respectively. Current Specify current in the following format: i[modifiers]([:modifiers]) where is a fully qualified device name.
Setting Up Analyses out device specifies the These building blocks can be used for specifying output variables as shown in Table 8-3 (which summarizes the accepted output variable formats) and Tables 8-4 through 8-7 (which list valid elements for two-terminal, three or fourterminal, transmission line devices, and AC specifications).
8-8 Setting Up Analyses and Starting Simulation Table 8-4 Element Definitions for 2-Terminal Devices Device Type < out id > or < out device > Device Indicator capacitor C Output Variable Examples V(CAP:1) I(CAP) diode D V(D23:1) I(D23) voltage-controlled voltage source E current-controlled current source F voltage-controlled current source G current-controlled voltage source H independent current source I inductor L V(E14:1) I(E14) V(F1:1) I(F1) V(G2:1) I(G2) V(HSOURCE:1) I(HSOURCE) V
Setting Up Analyses Table 8-5 8-9 Element Definitions for 3- or 4-Terminal Devices < out id > or < out device > Device Type Output Variable Examples D (Drain terminal) V(B11:D) G (Gate terminal) ID(B11) Device Indicato r GaAs MESFET B S (Source terminal) Junction FET J D (Drain terminal) VG(JFET) G (Gate terminal) I(JFET:G) S (Source terminal) MOSFET M B (Bulk, substrate terminal) VDG(M1) ID(M1) D (Drain terminal) G (Gate terminal) S (Source terminal) bipolar transistor Q B
8-10 Setting Up Analyses and Starting Simulation Table 8-7 Element Definitions for AC Analysis Specific Elements Device Symbol Meaning Output Variable Examples (none) magnitude (default) V(V1) I(V1) M magnitude VM(CAP1:1) IM(CAP1:1) DB magnitude in decibels VDB(R1) P phase IP(R1) R real part VR(R1) I imaginary part VI(R1) The INOISE, ONOISE, DB(INOISE), and DB(ONOISE) output variables are predefined for use with noise (AC sweep) analysis.
Starting Simulation Starting Simulation Once you have used MicroSim Schematics to enter your circuit design and to set up the analyses to be performed, you can start simulation by selecting Simulate from the Analysis menu. When you enter and set up your circuit this way, the files needed for simulation are automatically created by Schematics and the simulator is started from Schematics. There may be situations, however, when you want to run PSpice A/D outside of Schematics.
8-12 Setting Up Analyses and Starting Simulation Starting Simulation Outside of Schematics To start PSpice A/D outside of Schematics 1 Double-click on the PSpice A/D icon in the MicroSim Program Group. 2 Select Open from the File menu. 3 Do one of the following: • Double-click on the circuit file name in the list box. • Enter the name of the circuit file to be simulated in the File Name text box.
Starting Simulation Running simulations with multiple circuit files You can direct PSpice A/D to simulate multiple circuit files using one of the following methods. Method 1 1 Click on the PSpice A/D icon in the MicroSim program group. 2 Select Properties from the File menu. 3 Include the following switch in the command line: /wNO_NOTIFY This disables the message that pops up each time a simulation is completed. 4 Select Open from the File menu from the PSpice A/D status window.
8-14 Setting Up Analyses and Starting Simulation Circuit file names may be fully qualified or contain the wild card characters * and ?. The Simulation Status Window As PSpice A/D performs the circuit simulation, a status window is displayed so you can monitor the progress of the simulation. Figure 8-1 shows an example of the PSpice A/D status window.
Starting Simulation Menus The menus accessed from the menu bar include items to control the simulator and customize the window display characteristics. These are especially useful when invoking PSpice A/D directly. Simulation progress display The lower portion of the window displays the progress of each simulation as it proceeds.
DC Analyses 9 Chapter Overview This chapter describes how to set up DC analyses and includes the following sections: DC Sweep on page 9-2 Bias Point Detail on page 9-9 Small-Signal DC Transfer on page 9-11 DC Sensitivity on page 9-13
9-2 DC Analyses DC Sweep Minimum Requirements to Run a DC Sweep Analysis Minimum circuit design requirements Table 9-1 DC Sweep Circuit Design Requirements Swept Variable Type See Setting Up Analyses on page 8-3 for a description of the Analysis Setup dialog box. voltage source voltage source with a DC specification (VDC, for example) temperature none current source current source with a DC specification (IDC, for example) model parameter PSpice A/D model (.
DC Sweep 9-3 Overview of DC Sweep The DC sweep analysis causes a DC sweep to be performed on the circuit. DC sweep allows you to sweep a source (voltage or current), a global parameter, a model parameter, or the temperature through a range of values. The bias point of the circuit is calculated for each value of the sweep. This is useful for finding the transfer function of an amplifier, the high and low thresholds of a logic gate, and so on.
9-4 DC Analyses To calculate the DC response of an analog circuit, PSpice A/D removes time from the circuit. This is done by treating all capacitors as open circuits, all inductors as shorts, and using only the DC values of voltage and current sources. A similar approach is used for digital devices: all propagation delays are set to zero, and all stimulus generators are set to their time-zero values. In order to solve the circuit equations, PSpice A/D uses an iterative algorithm.
DC Sweep 9-5 Setting Up a DC Stimulus To run a DC sweep or small-signal DC transfer analysis, you need to place and connect one or more independent sources and then set the DC voltage or current level for each source. To set up a DC stimulus 1 Place and connect one of these symbols in your schematic: For voltage input Use this... VDC VSRC When you are running... A DC sweep and/or transfer function analysis only. Multiple analysis types including DC sweep and/or transfer function. When you are running.
9-6 DC Analyses Nested DC Sweeps A second sweep variable can be selected once a primary sweep value has been specified in the DC Sweep dialog box. When you specify a secondary sweep variable, it forms the outer loop for the analysis. That is, for every increment of the second sweep variable, the first sweep variable is stepped through its entire range of values. To set up a nested sweep 1 Click the Nested Sweep button in the DC Sweep dialog box.
DC Sweep 9-7 Curve Families for DC Sweeps Whenever a nested DC sweep is performed, the entire curve family is displayed. That is, the nested DC sweep is treated as a single Probe data section (or you can think of it as a single PSpice A/D run). For the circuit shown in Figure 9-3, you could set up a DC sweep analysis with an outer sweep of the voltage source VD and an inner sweep of the voltage source VG as listed in Table 9-2.
9-8 DC Analyses Figure 9-4 Device Curve Family Figure 9-5 Operating Point Determination for Each Member of the Curve Family
Bias Point Detail 9-9 Bias Point Detail Minimum Requirements to Run a Bias Point Detail Analysis Minimum circuit design requirements None. Minimum program setup requirements • In the Analysis Setup dialog box, select ( ✓) the Bias Point Detail check box to enable it. • Start the simulation as described in Starting Simulation on page 8-11. See Setting Up Analyses on page 8-3 for a description of the Analysis Setup dialog box.
9-10 DC Analyses When the Bias Point Detail analysis is enabled, the following information is reported to the output file: • a list of all analog node voltages • a list of all digital node states • the currents of all voltage sources and their total power • a list of the small-signal parameters for all devices If Bias Point Detail is enabled, you can suppress the reporting of the bias point analog and digital node values: 1 Select Setup from the Analysis menu.
Small-Signal DC Transfer 9-11 Small-Signal DC Transfer Minimum Requirements to Run a Small-Signal DC Transfer Analysis Minimum circuit design requirements • The circuit should contain an input source, such as VSRC. Minimum program setup requirements • In the Analysis Setup dialog box, click the Transfer Function button. In the Transfer Function dialog box, specify the name of the input source desired. See Output Variables on page 8-5 for a description of output variable formats.
9-12 DC Analyses Overview of Small-Signal DC Transfer The small-signal DC transfer analysis causes the small-signal transfer function to be calculated by linearizing the circuit around the bias point. The small-signal gain, input resistance, and output resistance are calculated and reported. The digital devices themselves are not included in the smallsignal analysis. A gate, for instance, does not have a frequency response.
DC Sensitivity 9-13 DC Sensitivity Minimum Requirements to Run a DC Sensitivity Analysis Minimum circuit design requirements None. Minimum program setup requirements • In the Analysis Setup dialog box, click the Sensitivity button. In the Sensitivity Analysis dialog box, enter the output variable desired. See Setting Up Analyses on page 8-3 for a description of the Analysis Setup dialog box. • If needed, in the Analysis Setup dialog box, select ( ✓) the Sensitivity check box to enable it.
9-14 DC Analyses Overview of DC Sensitivity DC sensitivity analysis calculates and reports the sensitivity of one node voltage to each device parameter for the following device types: • resistors • independent voltage and current sources • voltage and current-controlled switches • diodes • bipolar transistors The sensitivity is calculated by linearizing all devices around the bias point.
AC Analyses 10 Chapter Overview This chapter describes how to set up AC sweep and noise analyses. AC Sweep Analysis on page 10-2 describes how to set up an analysis to calculate the frequency response of your circuit. This section also discusses how to define an AC stimulus and how PSpice A/D treats nonlinear devices in an AC sweep. Noise Analysis on page 10-9 describes how to set up an analysis to calculate device noise contributions and total input and output noise.
10-2 AC Analyses AC Sweep Analysis What You Need to Do to Run an AC Sweep The following procedure describes the minimum set of things that you need to do to run an AC sweep analysis. For more detail on any step, go to the page referenced in the sidebar next to the step. To set up and run an AC sweep To find out how, see Setting Up an AC Stimulus on page 10-3. 1 Place and connect a voltage or current source with an AC input signal.
AC Sweep Analysis • Digital devices hold the states that PSpice A/D calculated when solving for the bias point. • Because AC sweep analysis is a linear analysis, it only considers the gain and phase response of the circuit; it does not limit voltages or currents. 10-3 The best way to use AC sweep analysis is to set the source magnitude to one. This way, the measured output equals the gain, relative to the input source, at that output.
10-4 AC Analyses 2 Double-click the symbol instance. A dialog box appears listing the attribute settings for the symbol instance. 3 Depending on the source symbol that you placed, define the AC specification as follows: For VAC or IAC Set this attribute... To this value... ACMAG AC magnitude in volts (for VAC) or amps (for IAC); units are optional. ACPHASE Optional AC phase in degrees. For VSRC or ISRC Set this attribute...
AC Sweep Analysis 10-5 Setting Up an AC Analysis To set up the AC analysis 1 From the Analysis menu, select Setup. 2 Click AC Sweep. 3 In the AC Sweep dialog box, choose the AC Sweep Type and set the number of sweep points as follows: To sweep frequency... Do this... linearly Choose Linear and set Total Pts to the total number of points in the sweep. logarithmically by octaves Choose Octave and set Pts/Octave to the total number of points per octave.
10-6 AC Analyses AC Sweep Setup in “example.sch” If you look at the example circuit, example.sch, provided with your MicroSim programs, you’ll find that its AC analysis is set up as shown in Figure 10-1. Figure 10-1 AC Analysis Setup for example.sch Note The source, V1, is a VSIN source that is normally used for setting up sine wave signals for a transient analysis. It also has an AC attribute so that you can also use it for an AC analysis.
AC Sweep Analysis 10-7 How PSpice A/D Treats Nonlinear Devices An AC Sweep analysis is a linear or small-signal analysis. This means that nonlinear devices must be linearized to run the analysis. What’s required to linearize a device If you were to manually linearize a device such as a transistor amplifier, you would need to do the following: 1 Compute the DC bias point for the circuit. 2 Compute the complex impedance and/or transconductance values for each device at this bias point.
10-8 AC Analyses Using a DC source Consider the circuit shown here. At the DC bias point, PSpice A/D calculates the partial derivatives which determine the linear response of the multiplier as follows: ∂V ( Out ) ∂V ( Out ) V ( Out ) = V ( In1 ) ⋅ --------------------- + V ( In2 ) ⋅ --------------------∂V ( In1 ) ∂V ( In2 ) = V ( In1 ) ⋅ V ( In2 ) + V ( In2 ) ⋅ V ( In1 ) where the terms in bold are calculated at the DC bias point.
Noise Analysis 10-9 Noise Analysis What You Need to Do to Run a Noise Analysis The following procedure describes the minimum set of things that you need to do to run a noise analysis. For more detail on any step, go to the page referenced in the sidebar next to the step. To set up and run an AC sweep 1 Place and connect a voltage or current source with an AC input signal. To find out how, see Setting Up an AC Stimulus on page 10-3. 2 Set up the AC sweep simulation specification.
10-10 AC Analyses What is Noise Analysis? When running a noise analysis, PSpice A/D calculates and reports the following for each frequency specified for the AC sweep analysis: • device noise, which is the noise contribution propagated to the specified output net from every resistor and semiconductor device in the circuit; for semiconductor devices, the device noise is also broken down into constituent noise contributions where applicable • total output and equivalent input noise Example: Diodes have
Noise Analysis 10-11 Setting Up a Noise Analysis To set up the noise analysis 1 From the Analysis menu, select Setup. 2 Click AC Sweep. 3 In the AC Sweep dialog box, set up an AC sweep analysis as described on page 10-5. 4 In the AC Sweep dialog box, select (✓) the Noise Enabled check box. 5 Enter the noise analysis parameters as follows: In this text box... Output Voltage Type this... A voltage output variable of the form V(node, [node]) where you want the total output noise calculated.
10-12 AC Analyses Analyzing Noise in Probe For a break down of noise output variables by supported device type, see Table 17-9 on page 17-52. Probe supports these output variable formats, which you can use to view traces for device noise contributions and total input or output noise at every frequency in the analysis. To view this... Flicker noise for a device Shot noise for a device Use this output variable... Which is represented by this equation*...
Noise Analysis 10-13 About noise units This type of noise output variable... Device contribution of the form Nxxx Total input or output noise of the form V(ONOISE) or V(INOISE) Is reported in these units... 2 ( volts ) ⁄ ( Hz ) ( volts ) ⁄ ( Hz ) Example You can run a noise analysis on the circuit shown in Figure 10-1 on page 10-6. To run a noise analysis on the example: 1 In Schematics, open the example.sch circuit provided with your MicroSim programs in the Examples\Schemat\Example subdirectory.
10-14 AC Analyses To find out more about Probe macros, refer to Probe online help. Figure 10-2 shows Probe traces for Q1’s constituent noise sources as well as total nose for the circuit after simulating. Notice that the trace for RMSSUM (at the top of the plot), which is a macro for the trace expression SQRT(NTOT(Q1) + NTOT(Q2) + NTOT(Q3) + ... ), exactly matches the total output noise, V(ONOISE), calculated by PSpice A/D. Figure 10-2 Device and Total Noise Traces for “example.
Transient Analysis 11 Chapter Overview This chapter describes how to set up a transient analysis and includes the following sections: Overview of Transient Analysis on page 11-2 Defining a Time-Based Stimulus on page 11-3 Transient (Time) Response on page 11-15 Internal Time Steps in Transient Analyses on page 11-17 Switching Circuits in Transient Analyses on page 11-18 Plotting Hysteresis Curves on page 11-18 Fourier Components on page 11-20
11-2 Transient Analysis Overview of Transient Analysis Minimum Requirements to Run a Transient Analysis Minimum circuit design requirements Circuit should contain one of the following: • an independent source with a transient specification (see Table 11-1) • an initial condition on a reactive element • a controlled source that is a function of time Minimum program setup requirements See Setting Up Analyses on page 8-3 for a description of the Analysis Setup dialog box.
Defining a Time-Based Stimulus 11-3 Defining a Time-Based Stimulus Overview of Stimulus Generation Symbols that generate input signals for your circuit can be divided into two categories: • those whose transient behavior is characterized graphically using the Stimulus Editor • those whose transient behavior is characterized by manually defining their attributes within Schematics Note PSpice A/ D Basics+ does not include the Stimulus Editor. Their symbols are summarized in Table 11-1.
11-4 Transient Analysis Table 11-1 Stimulus Symbols for Time-Based Input Signals Specified by... Symbol Name Description ISRC IEXP IPULSE IPWL IPWL_RE_FOREVER IPWL_F_RE_FOREVER IPWL_N_TIMES IPWL_F_N_TIMES ISFFM ISIN current sources DIGCLOCK digital clock signal STIM1 STIM4 STIM8 STIM16 digital stimuli FSTIM digital file stimulus To use any of these source types, you must place the symbol in your schematic and then define its transient behavior.
The Stimulus Editor Utility 11-5 MicroSim Schematics MicroSim PSpice A/D MicroSim Stimulus Editor input waveforms stimulus files Figure 11-1 Relationship of Stimulus Editor with Schematics and PSpice A/D The stimulus specification created using the Stimulus Editor is saved to a file, automatically configured into the schematic, and associated with the corresponding VSTIM, ISTIM, or DIGSTIM part instance or symbol definition.
11-6 Transient Analysis Stimulus Files The Stimulus Editor produces a file containing the stimuli with their transient specification. These stimuli are defined as simulator device declarations using the V (voltage source), I (current source), and U STIM (digital stimulus generator) forms. Since the Stimulus Editor produces these statements automatically, you will never have to be concerned with their syntax.
The Stimulus Editor Utility 11-7 Starting the Stimulus Editor The Stimulus Editor is fully integrated with Schematics and can be run from either the schematic editor or symbol editor. You can start the Stimulus Editor by the following methods: • Double-click a stimulus instance • Select one or more stimulus instances in the schematic and select Stimulus from the Edit menu. • Select Edit Stimulus from the Analysis menu.
11-8 Transient Analysis See Chapter 14,Digital Simulation, for detailed information about creating digital stimuli. Defining Stimuli 1 Place stimulus part instances from the symbol set: VSTIM, ISTIM, interface ports (IF_IN and INTERFACE), and DIGSTIM. 2 Double-click the source instance to start the Stimulus Editor. When you are asked whether you want to edit the named stimulus, click OK. 3 Fill in the transient specification according to the dialogs and prompts.
The Stimulus Editor Utility 11-9 8 Move the cursor to (200ns, 1) and click the left mouse button. This adds the point. Notice that there is automatically a point at (0,0). Ignore it for now and continue to add a couple more points to the right of the current one. 9 Click-right to stop adding points. 10 Select Save from the File menu. If you make a mistake or want to make any changes, reshape the trace by dragging any of the handles to a new location.
11-10 Transient Analysis 7 8 9 b Enter {AMP} for Amplitude. The curly braces are required. They indicate that the expression needs to be evaluated at simulation time. c Enter 10k for Frequency and click OK. d Select Save from the File menu. Within Schematics, place and define the PARAM symbol: a Select Get New Part from the Draw menu. b Either browse special.slb for the PARAM symbol or type in the name. c Place the symbol on your schematic and double-click it to edit the attributes.
The Stimulus Editor Utility STIMTYPE type of stimulus; valid values are ANALOG or DIGITAL; if this attribute is nonexistent, the stimulus is assumed to be ANALOG STIMULUS name of the stimulus model 2 Select Stimulus from the Edit menu. Schematics searches the configured list of global stimulus files. If you are creating a new stimulus symbol and the stimulus is not found, you are prompted for the name of the stimulus file in which the new definition should be saved.
11-12 Transient Analysis Editing a Stimulus To edit an existing stimulus PWL stimuli are a little different since they are a series of time/ value pairs. This provides a fast way to scale a PWL stimulus. 1 Start the Stimulus Editor and select Get from the Stimulus menu. 2 Double-click the trace name (at the bottom of the X axis for analog and to the left of the Y axis for digital traces.
The Stimulus Editor Utility Deleting and Removing Traces To delete a trace from the displayed screen, select the trace name by clicking on its name, then press X. This will only erase the display of the trace, not delete it from your file. The trace is still available by selecting Get from the Stimulus menu. To remove a trace from a file, select Remove from the Stimulus menu. Note Once a trace is removed, it is no longer retrievable. Delete traces with caution.
11-14 Transient Analysis 4 In the schematic editor, configure the Stimulus Editor’s output file into your schematic: a Select Library and Include Files from the Analysis menu. b Enter the file name specified in step 2. c If the stimulus specifications are for local use in the current schematic, click the Add Stimulus (or Add Include) button. For global use by a symbol in the Symbol Library or by any schematic, use Add Stimulus* (or Add Include*) instead. d Click OK.
Transient (Time) Response 7 11-15 To change stimulus references globally for a symbol: a Select Edit Library from the File menu to start the symbol editor.
11-16 Transient Analysis The example circuit example.sch is provided with the MicroSim program installation. Figure 11-3 Example Schematic example.sch The transient analysis does its own calculation of a bias point to start with, using the same technique as described for DC sweep. This is necessary because the initial values of the sources can be different from their DC values.
Internal Time Steps in Transient Analyses 11-17 Internal Time Steps in Transient Analyses During analog analysis, PSpice A/D maintains an internal time step which is continuously adjusted to maintain accuracy while not performing unnecessary steps. During periods of inactivity, the internal time step is increased. During active regions, it is decreased. The maximum internal step size can be controlled by specifying so in the Step Ceiling text box in the Transient dialog.
11-18 Transient Analysis Switching Circuits in Transient Analyses Running transient analysis on switching circuits can lead to long run times. PSpice A/D must keep the internal time step short compared to the switching period, but the circuit’s response extends over many switching cycles. This technique is described in: V. Bello, “Computer Program Adds SPICE to SwitchingRegulator Analysis,” Electronic Design, March 5, 1981.
Plotting Hysteresis Curves * Schematics Netlist R_RIN 1 2 50 R_RC1 0 3 50 R_R1 3 5 185 R_R2 5 8 760 R_RC2 0 6 100 R_RE 4 8 260 R_RTH2 7 0 85 C_CLOAD 0 7 5PF V_VEE 8 0 dc -5 V_VIN 1 0 +PWL 0 -8 1MS -1.0V 2MS -1.8V R_RTH1 8 7 125 Q_Q1 3 2 4 QSTD Q_Q2 6 5 4 QSTD Q_Q3 0 6 7 QSTD Q_Q4 0 6 7 QSTD Figure 11-5 Netlist for Schmitt Trigger Circuit The QSTD model is defined as: .MODEL QSTD NPN( is=1e-16 bf=50 br=0.1 rb=50 rc=10 tf=.12ns tr=5ns + cje=.4pF pe=.8 me=.4 cjc=.5pF pc=.8 mc=.
11-20 Transient Analysis Figure 11-6 Hysteresis Curve Example: Schmitt Trigger Fourier Components Fourier analysis is enabled through the transient analysis setup dialog box. Fourier analysis calculates the DC and Fourier components of the result of a transient analysis. By default, the 1st through 9th components are computed, however, more can be specified. You must do a transient analysis in order to do a Fourier analysis.
Fourier Components In the example Fourier analysis specification shown in Figure 11-2 on page 11-15, the voltage waveform at node OUT2 from the transient analysis is to be used and the fundamental frequency is to be 1 megahertz for the harmonic decomposition. The period of fundamental frequency is 1 microsecond (inverse of the fundamental frequency). Only the last 1 microsecond of the transient analysis is used, and that portion is assumed to repeat indefinitely.
Parametric and Temperature Analysis 12 Chapter Overview This chapter describes how to set up parametric and temperature analyses. Parametric and temperature are both simple multi-run analysis types.
12-2 Parametric and Temperature Analysis not included in: Parametric Analysis Minimum Requirements to Run a Parametric Analysis Minimum circuit design requirements • Set up the circuit according to the swept variable type as listed in Table 12-1. • Set up a DC sweep, AC sweep, or transient analysis. Table 12-1 Parametric Analysis Circuit Design Requirements Swept Variable Type See Setting Up Analyses on page 8-3 for a description of the Analysis Setup dialog box.
Parametric Analysis Overview of Parametric Analysis Parametric analysis performs multiple iterations of a specified standard analysis while varying a global parameter, model parameter, component value, or operational temperature. The effect is the same as running the circuit several times, once for each value of the swept variable. See Parametric Analysis on page 2-24 for a description of how to set up a parametric analysis.
12-4 Parametric and Temperature Analysis This series of PSpice A/D runs varies the value of resistor R1 from 0.5 to 1.5 ohms in 0.1 ohm steps. Since the time-constant of the circuit is about one second, we perform a transient analysis of approximately 20 seconds. Create the circuit in MicroSim Schematics by placing a piecewise linear independent current source (IPWL from source.slb). Set the current source attributes as follows: AC T1 I1 T2 I2 T3 I3 = = = = = = = 1a 0s 0a 10ms 0a 10.
Parametric Analysis 12-5 Using performance analysis to plot overshoot and rise time After performing the PSpice A/D simulation that creates the data file called rlcfilt.dat, you can run Probe to compute the specified performance analysis goal functions. When Probe is started, you are presented with a list of all the sections or runs in the Probe data file produced by PSpice A/D. To use the data from every run, select All and click OK in the Available Selections dialog box.
12-6 Parametric and Temperature Analysis genrise( I(L1) ) In Figure 12-3, we can see how the rise time decreases as the damping resistance increases for the filter. Another Y axis can be added to the plot for the overshoot of the current through L1 by selecting Add Y Axis from the Plot menu. The Y axis is immediately added. We now select Add from the Trace menu and enter: overshoot( I(L1) ) Figure 12-3 shows how the overshoot increases with increasing resistance. Figure 12-3 Rise Time and Overshoot vs.
Parametric Analysis Now we can use the multiple X axes feature to view the original waveform family for inductor L1 current along with the derived rise time and overshoot data. We must first add a new plot by selecting Add Plot from the Plot menu. To set this plot’s X axis to a unique scale, select Unsync Plot from the Plot menu. You’ll notice that the new plot’s X axis is now labeled with range and variable information.
12-8 Parametric and Temperature Analysis Example: Frequency Response vs. Arbitrary Parameter A common request is to view a plot of the linear response of a circuit at a specific frequency as one of the circuit parameters varies (such as the output of a band pass filter at its center frequency vs. an inductor value). In this example, the value of a nonlinear capacitance is measured using a 10 kHz AC signal and plotted vs. its bias voltage.
Parametric Analysis Displaying results in Probe Use Probe to display the capacitance calculated at the frequency of interest vs. the stepped parameter. After analyzing the circuit with PSpice A/D: 1 Run Probe. 2 Load all AC analysis sections. 3 Select Add from the Trace menu. 4 Add the following trace expression: IMG(-I(Vin)/V(1,0))/(2*3.1416*Frequency) Or add the expression: CvF(-I(Vin)/V(1,0)) Where CvF is a macro which measures the effective capacitance in a complex conductance.
12-10 Parametric and Temperature Analysis 6 In the X value text box, type 10K. 7 Click Next>. The wizard displays the gain trace for the first run to text the goal function (YatX). 8 Click Finish. The resultant Probe plot is shown in Figure 12-6. Figure 12-6 Probe Plot of Capacitance vs.
Temperature Analysis 12-11 Temperature Analysis Minimum Requirements to Run a Temperature Analysis Minimum circuit design requirements None. Minimum program setup requirements • In the Analysis Setup dialog box, click the Temperature button. Specify the temperature or list of temperatures in the Temperature Analysis dialog box. • If needed, in the Analysis Setup dialog box, select ( ✓) the Temperature check box to enable it. • Start the simulation as described in Starting Simulation on page 8-11.
12-12 Parametric and Temperature Analysis are recomputed based upon the CRES model which has parameters TC1 and TC2 reflecting linear and quadratic temperature dependencies. Likewise, the Q3 and Q4 device values are recomputed using the Q2N2222 model which also has temperature-dependent parameters. In the simulation output file, these recomputed device values are reported in the section labeled TEMPERATURE ADJUSTED VALUES. The example circuit example.
Monte Carlo and Sensitivity/ Worst-Case Analyses 13 Chapter Overview This chapter describes how to set up Monte Carlo and sensitivity/worst-case analyses and includes the following sections: Statistical Analyses on page 13-2 Monte Carlo Analysis on page 13-7 Worst-Case Analysis on page 13-25 This entire chapter describes features that are not included in PSpice A/D Basics+.
13-2 Monte Carlo and Sensitivity/Worst-Case Analyses not included in: Statistical Analyses Monte Carlo and sensitivity/worst-case are statistical analyses. This section describes information common to both types of analyses. See Monte Carlo Analysis on page 13-7 for information specific to Monte Carlo analyses, and see Worst-Case Analysis on page 13-25 for information specific to sensitivity/worst-case analyses.
Statistical Analyses Output Control for Statistical Analyses Monte Carlo and sensitivity/worst-case analyses can generate the following types of reports: • model parameter values used for each run (that is, the values with tolerances applied) • waveforms from each run, as a function of specifying data collection, or by specifying output variables in the analysis set up • summary of all the runs using a collating function Output is saved to the Probe data file for use by the Probe graphical waveform a
13-4 Monte Carlo and Sensitivity/Worst-Case Analyses Waveform Reports For Monte Carlo analyses, there are four variations of the output which can be specified in the Output section of the Monte Carlo or Worst Case dialog. These options are: In excess of about 10 runs, the Probe display tends to become more of a band than a set of individual waveforms. This can be useful for seeing the typical spread for a particular output variable.
Statistical Analyses Table 13-1 Collating Functions Used in Statistical Analyses Function Description MIN find the minimum value of each waveform RISE_EDGE find the first occurrence of the waveform crossing above a specified threshold value FALL_EDGE find the first occurrence of the waveform crossing below a specified threshold value 13-5
13-6 Monte Carlo and Sensitivity/Worst-Case Analyses Temperature Considerations in Statistical Analyses Refer to Temperature Effects on Monte Carlo Analysis in the Application Notes manual for more information on this topic. The statistical analyses perform multiple runs, as does the temperature analysis. Conceptually, the Monte Carlo and worstcase loops are inside the temperature loop.
Monte Carlo Analysis Monte Carlo Analysis The Monte Carlo analysis computes the circuit response to changes in component values by randomly varying all of the device model parameters for which a tolerance is specified. This provides statistical data on the impact of a device parameter’s variance. 13-7 not included in: With Monte Carlo analysis model parameters are given tolerances, and multiple analyses (DC, AC, or transient) are run using these tolerances.
13-8 Monte Carlo and Sensitivity/Worst-Case Analyses PSpice A/D starts as usual by running all of the analyses enabled in the Analysis Setup dialog with all parameters set to their nominal values. However, with Monte Carlo enabled, the DC sweep analysis results are saved for later reference and comparison. After the nominal analyses are finished, more of the specified analysis runs are performed (DC sweep in this example).
Monte Carlo Analysis 13-9 Figure 13-4 Parameter Values for Monte Carlo Pass 3 There is a trade-off in choosing the number of Monte Carlo runs. More runs provide better statistics, but take proportionally more computer time. The amount of computer time scales directly with the number of runs: 20 transient analyses take 20 times as long as one transient analysis. During Monte Carlo runs, the PSpice A/D status display includes a line showing the run number and the total number of runs to be done.
13-10 Monte Carlo and Sensitivity/Worst-Case Analyses Tutorial: Monte Carlo Analysis of a Pressure Sensor In this tutorial, you will see how the performance of a pressure sensor circuit with a pressure-dependent resistor bridge is affected by manufacturing tolerances. You will use Monte Carlo analysis features provided in Schematics and PSpice A/D to explore these effects. Drawing the schematic To begin, construct the bridge as shown in the schematic in Figure 13-5.
Monte Carlo Analysis • Place the analog ground using the AGND symbol. • To connect the symbols, use Wire from the Draw menu. • To move values and/or reference designators, click the value or reference designator to select it, then drag it to the new location. 13-11 or press C+W Defining component values Define the component values as shown in Figure 13-5. For the pressure sensor, you need to do the following: • Change the resistor values for R3, R5, R6, and R7 from their 1K default.
13-12 Monte Carlo and Sensitivity/Worst-Case Analyses press J 4 Click Save Attr to accept the changes. 5 Click Change Display. 6 In the What to Display frame, choose the Value Only option to make the DC value (1.35v) visible on the schematic. 7 Click OK to accept the change, then click OK again to exit the attributes dialog box. Setting up the parameters To complete the value specification for R3, define the global parameters: Pcoeff, P, and Pnom.
Monte Carlo Analysis 13-13 Using resistors with models To explore the effects of manufacturing tolerances on the behavior of this circuit, you will set device (DEV) and (LOT) tolerances on the model parameters for resistors R1, R2, R3, and R4 in a later step (see page 13-14). This means you need to use resistor symbols that have model associations. Because R symbols do not have an associated model (and therefore no model parameters), change the resistor symbols to Rbreak symbols which do have a a model.
13-14 Monte Carlo and Sensitivity/Worst-Case Analyses Saving the schematic Before editing the models for the Rbreak resistors, save the schematic. To save the schematic 1 From the File menu, select Save As. 2 In the File Name text box, type psensor.sch. 3 Click OK. Defining tolerances for the resistor models The model editor lets you change the .MODEL or .SUBCKT syntax for a model definition. To find out more about the model editor, see Using the Model Editor on page 4-29.
Monte Carlo Analysis 13-15 names it -X, which in this tutorial, is Rbreak-X. In the model editor, you can change this name to whatever you want. 4 5 To change the instance model name from Rbreak-X to Rmonte1, do the following: a In the model editor window, double-click Rbreak-X in the .model Rbreak-X RES line. b Type RMonte1. To add a 2% device tolerance and a 10% lot tolerance to the resistance multiplier, do the following: a Change the R=1 line following the .
13-16 Monte Carlo and Sensitivity/Worst-Case Analyses To have resistors R2 and R4 use the same tolerances as R1 1 Select R2. 2 From the Edit menu, select Model. 3 Click Change Model Reference. 4 Type RMonte1. 5 Repeat steps 1-4 for R4. To assign 5% device tolerance to the resistance multiplier for R3 1 Select R3. 2 From the Edit menu, select Model. 3 Click Edit Instance Model (Text). 4 Change the instance model name in the .MODEL statement to RTherm.
Monte Carlo Analysis Setting up the analyses Define and enable a DC analysis that sweeps the pressure value, and a Monte Carlo analysis that runs the DC sweep with each change to the resistance multipliers. To set up the DC sweep 1 From the Analysis menu, select Setup. 2 Click DC Sweep. 3 In the Swept Var. Type frame, select Global Parameter. 4 Type values in the relevant text boxes as follows. 5 In this text box... Type this... Name P Start Value 0 End Value 5.0 Increment 0.1 Click OK.
13-18 Monte Carlo and Sensitivity/Worst-Case Analyses To verify that the DC sweep and Monte Carlo analyses are enabled 1 In the Analysis Setup dialog box, make sure that the check box next to the DC Sweep and to the Monte Carlo/Worst Case buttons are selected ( ✓). If not, click them to enable the analyses. 2 Click OK. Running the analysis and viewing the results Run the simulation and analyze the results in Probe.
Monte Carlo Analysis Monte Carlo Histograms A typical application of Monte Carlo analysis is predicting yields on production runs of a circuit. Probe can be used to display data derived from Monte Carlo waveform families as histograms, part of Probe’s performance analysis feature. To illustrate this feature, we will simulate a fourth order Chebyshev active filter, running a series of 100 AC analyses while randomly varying resistor and capacitor values for each run.
13-20 Monte Carlo and Sensitivity/Worst-Case Analyses Figure 13-8 Chebyshev Filter Setting up the analysis To analyze our filter, we will set up both an AC analysis and a Monte Carlo analysis. The AC analysis sweeps 50 points per decade from 100 Hz to 1 MHz. The Monte Carlo analysis is set to take 100 runs (see Figure 13-9). The analysis type is AC and the output variable that we are interested in is V(OUT). We will select All in the MC Options box.
Monte Carlo Analysis 13-21 To run the simulation and load Probe with data 1 From the Analysis menu, select Simulate. or press ! When complete, Probe automatically starts. Because PSpice A/D ran a Monte Carlo analysis, PSpice A/D saved multiple runs or sections of data. These are listed in the Available Sections dialog box. 2 In Probe, in the Available Sections dialog box, click All, and then OK. To display a histogram for the 1 dB bandwidth 1 In Probe, from the Plot menu, select X Axis Settings.
13-22 Monte Carlo and Sensitivity/Worst-Case Analyses 3 Click Save and then OK. The histogram for 1 dB bandwidth is shown in Figure 13-10.
Monte Carlo Analysis The statistics for the histogram are displayed along the bottom of the display. The statistics show the number of Monte Carlo runs, the number of divisions or vertical bars that make up the histogram, mean, sigma, minimum, maximum, 10th percentile, median, and 90th percentile. Ten percent of the goa1 function values are less than or equal to the 10th percentile number, and 90% of the goal function values are greater than or equal to that number.
13-24 Monte Carlo and Sensitivity/Worst-Case Analyses Figure 13-11 Center Frequency Histogram
Worst-Case Analysis Worst-Case Analysis This section discusses the analog worst-case analysis feature of PSpice A/D. The information provided in this section will help you to apply it properly and with realistic expectations. Overview of Worst-Case Analysis Worst-case analysis is used to find the worst probable output of a circuit or system given the restricted variance of its parameters.
13-26 Monte Carlo and Sensitivity/Worst-Case Analyses Analog behavioral models can be used to measure waveform characteristics other than those detected by the available collating functions, such as rise time or slope. Analog behavioral models can also be used to incorporate several voltages and currents into one output variable to which a collating function may be applied. See Chapter 6,Analog Behavioral Modeling, for more information.
Worst-Case Analysis model parameter. If a .PROBE statement is included in the circuit file, then the results of the nominal and worst-case runs are saved for viewing with Probe. An important condition for correct worst-case analysis Worst-case analysis is not an optimization process; it does not search for the set of parameter values which result in the worst result.
13-28 Monte Carlo and Sensitivity/Worst-Case Analyses Worst-Case Analysis Example The schematic shown in Figure 13-12 is for an amplifier circuit which is a biased BJT. This circuit is used to demonstrate how a simple worst-case analysis works. It also shows how nonmonotonic dependence of the output on a single parameter can adversely affect the worst-case analysis.
Worst-Case Analysis 13-29 conditions under which worst-case analysis works well and those that can produce misleading results when output is not monotonic with a variable parameter (see Figure 13-15 and Figure 13-16). For demonstration, the parametric analysis is run first, generating the curve shown in Figure 13-15 and Figure 13-16. This curve, derived using the YatX goal function shown in Figure 13-13, illustrates the non-monotonic dependence of gain on Rb2.
13-30 Monte Carlo and Sensitivity/Worst-Case Analyses * Worst-case analysis comparing monotonic and non-monotonic * output with a variable parameter .lib ***** Input signal and blocking capacitor ***** Vin In 0 ac 1 Cin In B 1u ***** "Amplifier" ***** * gain increases with small increase in Rb2, but * device saturates if Rb2 is maximized. Vcc Vcc 0 10 Rc Vcc C 1k Q1 C B 0 Q2N2222 Rb1 Vcc B 10k Rb2 B 0 Rbmod 720 .model Rbmod res(R=1 dev 5%) ; WC analysis results ; are correct * .model Rbmod res(R=1.
Worst-Case Analysis 13-31 Output is monotonic within the tolerance range. Sensitivity analysis correctly points to the minimum value. Figure 13-15 Correct Worst-Case Results Output is non-monotonic within the tolerance range, thus producing incorrect worst-case results.
13-32 Monte Carlo and Sensitivity/Worst-Case Analyses Hints and Other Useful Information VARY BOTH, VARY DEV, and VARY LOT Figure 13-17 Schematic Demonstrating Use of VARY BOTH When VARY BOTH is specified in the .WC statement and a model parameter is specified with both DEV and LOT tolerances defined, the worst-case analysis may produce unexpected results.
Worst-Case Analysis manually adjust the nominal model parameter values according to the results, then perform another analysis with VARY DEV specified. Gaussian distributions Parameters using Gaussian distributions are changed by 3σ (three times sigma) for the worst-case analysis. YMAX collating function The purpose of the YMAX collating function is often misunderstood. This function does not try to maximize the deviation of the output variable value from nominal.
13-34 Monte Carlo and Sensitivity/Worst-Case Analyses Manual optimization Worst-case analysis can be used to perform manual optimization with PSpice A/D. The monotonicity condition is usually met if the parameters have a very limited range. Performing worst-case analysis with tight tolerances on the parameters yields sensitivity and worst-case results (in the output file) which can be used to decide how the parameters should be varied to achieve the desired response.
Worst-Case Analysis Using Monte Carlo analysis with YMAX is a good way to obtain a conservative guess at the maximum possible deviation from nominal, since worst-case analysis usually cannot provide this information.
Digital Simulation 14 Chapter Overview This chapter describes how to set up a digital simulation analysis and includes the following sections: What Is Digital Simulation? on page 14-2 Steps for Simulating Digital Circuits on page 14-2 Concepts You Need to Understand on page 14-3 Defining a Digital Stimulus on page 14-5 Defining Simulation Time on page 14-20 Adjusting Simulation Parameters on page 14-20 Starting the Simulation on page 14-22 Analyzing Results on page 14-23
14-2 Digital Simulation What Is Digital Simulation? Digital simulation is the analysis of logic and timing behavior of digital devices over time. PSpice A/D simulates this behavior during transient analysis. When computing the bias point, PSpice A/D considers the digital devices in addition to any analog devices in the circuit. See Tracking Timing Violations and Hazards on page 14-28 for information about persistent hazards, and for descriptions of the messages.
Concepts You Need to Understand 14-3 Concepts You Need to Understand States When the circuit is in operation, digital nodes take on values or output states shown in Table 14-1. Each digital state has a strength component as well.
14-4 Digital Simulation Strengths For additional information on this topic see Defining Output Strengths on page 7-21of Chapter 7,Digital Device Modeling. When a digital node is driven by more than one device, PSpice A/D must determine the correct level of the node. Each output has a strength value, and PSpice A/D compares the strengths of the outputs driving the node. The strongest driver determines the resulting level of the node.
Defining a Digital Stimulus Defining a Digital Stimulus A digital stimulus defines input to the digital portions of your circuit, playing a similar role to that played by the independent voltage and current sources for the analog portion of your circuit. The following table summarizes the digital stimulus devices provided in the symbol libraries. If you want to specify the input signal by... Then use this symbol... For this type of digital input...
14-6 Digital Simulation not included in: Using Top-Level Interface Ports Interface ports have two uses. You can use them to define: • connections only • stimuli and connections To enable using interface ports for stimuli 1 In Schematics, from the Options menu, select Restricted Operations. 2 In the Stimulus Options frame, select (✓) both check boxes. 3 Click OK. You are now ready to define digital stimuli. The stimuli you define for a particular schematic are stored in a stimulus file (.stl).
Defining a Digital Stimulus To start the Stimulus Editor with default stimuli for ALL top-level interface ports 1 In Schematics, place interface ports (INTERFACE or IF_IN) to define the inputs at the top level of the design. 2 From the Analysis menu, select Edit Stimuli. This creates entries (if they don’t already exist) in the design’s stimulus library for each interface port, and then starts the Stimulus Editor.
14-8 Digital Simulation not included in: Using the DIGSTIM Symbol The DIGSTIM stimulus symbol allows you to define a stimulus for a net or bus using the Stimulus Editor. To use the DIGSTIM symbol 1 Place and connect the DIGSTIM stimulus symbol to a wire or bus on your schematic. 2 Double-click the stimulus instance. This starts the Stimulus Editor. A dialog box appears asking you whether you want to edit the named stimulus. not included in: 3 Click OK.
Defining a Digital Stimulus 5 6 Enter values for the clock signal properties as described below. Enter this... Frequency clock rate Duty Cycle percent of high versus low in decimal or integer units Frequency = 20Meg Initial Value starting value: 0 or 1 Duty Cycle = 0.
14-10 Digital Simulation To add a transition When you have selected a transition to edit, a red handle appears. 1 In the Stimulus Editor, from the Edit menu, select Add. 2 Click the digital stimulus you want to edit. 3 Drag the new transition to its proper location on the waveform. 4 If you want to add more transitions, repeat steps 2 and 3. 5 When you are finished, right-click to exit the edit mode. To move a transition 1 Click the transition you want to move.
Defining a Digital Stimulus 14-11 To delete a transition 1 Click the transition you want to delete. 2 If needed, press V+click to select additional transitions on the same signal or different signals. 3 From the Edit menu, select Delete. Defining bus transitions The steps to create a bus are: 1 Create the digital bus stimulus. 2 Introduce transitions. 3 Optionally define the radix for bus values. These steps are described in detail in the following procedures.
14-12 Digital Simulation To introduce transitions (method 1) 1 In the Stimulus Editor, from the Edit menu, select Add. 2 In the digital value field on the toolbar (just right of the Add button), type a bus value in any of the following ways: To get this effect... Type this... Example: 12 A literal value [;radix] Example: +12;H An increment +[;radix] Example: -12;O A decrement -[;radix] To find out about valid radix values, see page 14-26.
Defining a Digital Stimulus 14-13 8 Click OK. 9 Repeat steps 4 through 8 for each transition. To set the default bus radix 1 From the Tools menu, select Options. 2 In the Bus Display Defaults frame, in the Radix list, select the radix you want as default. 3 Select this radix... To show values in this notation... Binary base 2 Octal base 8 Decimal base 10 Hexadecimal base 16 Click OK.
14-14 Digital Simulation Adding loops Suppose you have a stimulus that looks like this: A B and you want to create a stimulus that consists of three consecutive occurrences of the sequence that starts at A and ends at B: You can do this by using the MicroSim Text Editor to edit a stimulus library file. Within this file is a sequence of transitions that produces the original waveform. With the Text Editor you can modify the stimulus definition so it repeats itself.
Defining a Digital Stimulus 14-15 6 In the document that appears, find the set of consecutive lines comprising the sequence that you want to repeat. Each relevant line begins with the time of the transition and ends with a value or change in value. 7 Ahead of these lines, insert a line that uses this syntax: + Repeat for n_times where n_times is one of the following: 8 • A positive integer representing the number of repetitions.
14-16 Digital Simulation Using the DIGCLOCK Symbol To find out how to define a clock signal using the Stimulus Editor with interface ports or the DIGSTIM symbol, see Defining clock transitions on page 14-8. The DIGCLOCK symbol is way to define a clock signal by defining the symbol’s attributes. To define a clock signal using DIGCLOCK 1 Place and connect a DIGCLOCK symbol. 2 Double-click the symbol instance. 3 Define the attributes as described here: For this attribute... Specify this...
Defining a Digital Stimulus 14-17 Table 14-2 STIMn Part Attributes Attribute Description WIDTH Number of output signals (nodes). FORMAT Sequence of digits defining the number of signals corresponding to a digit in any term appearing in a COMMANDn attribute definition. Each digit must be either 1, 3, or 4 (binary, octal, hexadecimal, respectively); the sum of all digits in FORMAT must equal WIDTH. IO_MODEL I/O model describing the stimulus’ driving characteristics.
14-18 Digital Simulation Refer to the online MicroSim PSpice A/D Reference Manual Using the FILESTIM Device for more information about creating digital stimulus specifications and files. FILESTIM has a single pin for connection to the rest of the circuit. The digital stimulus specification must be defined in an external file. Using this technique, stimulus definitions can be created from scratch or extracted with little modification from another simulation’s output file.
Defining a Digital Stimulus 14-19 Figure 14-1 Schematic Fragment with FILESTIM The following steps set up the U2 stimulus so that the 74393 counter is cleared after 40 nsec have elapsed in a transient analysis: 1 Create a stimulus file named, for instance, reset.stm: Reset 0ns 1 40ns 0 The header line contains the names of all signals described in the file. In this case, there is only one: Reset. The remaining lines are the state transitions output for the signals named in the header.
14-20 Digital Simulation Defining Simulation Time To set up the transient analysis 1 In Schematics, from the Analysis menu, select Setup. 2 Click Transient. 3 In the Final Time text box, type the duration of the transient analysis. 4 Click OK. 5 Before exiting the Analysis Setup dialog box, make sure that the Transient check box is selected (✓). 6 Click Close.
Adjusting Simulation Parameters Selecting Propagation Delays All of PSpice A/D’s digital devices, including the primitives and library models, perform simulations using either minimum, typical, maximum, or worst-case (min/max) timing characteristics. You can select the delay circuit-wide or on individual device instances.
14-22 Digital Simulation Refer to the online MicroSim PSpice A/D Reference Manual Initializing Flip-Flops for more information about flipflops and latches. To initialize all flip-flops and latches 1 Note that the X initialization is the safest setting, since many devices do not power up to a known state. However, the 0 and 1 settings are useful in situations where the initial state of the flipflop is unimportant to the function of the circuit, such as a toggle flip-flop in a frequency divider.
Analyzing Results 14-23 Analyzing Results MicroSim Probe is the waveform analyzer for PSpice A/D simulations. Probe allows you to observe and manipulate interactively the waveform data produced by circuit simulation. For mixed analog/digital simulations, Probe can display analog and digital waveforms simultaneously with a common time base. PSpice A/D generates two forms of output: the simulation output file and the Probe data file.
14-24 Digital Simulation • Use spaces or commas to separate the output variables you place in the Trace Expressions list. You can also type trace expression directly into the Trace Expression text box. A typical set of entries might be: IN1 IN2 Q1 Q2 3 Click OK. Waveforms for the selected output variables appear on the screen.
Analyzing Results This placeholder... Means this...
14-26 Digital Simulation Adding Buses to a Probe Plot A set of up to 32 signals can be evaluated and displayed as a bus even if the selected signals were not originally a bus. This is done by following the same procedure already given for adding digital signals to the plot. However, when adding a bus, be sure to enclose the list of signals in braces: { }.
Analyzing Results 14-27 To add a bus expression Examples: 1 In the Add Trace dialog box, in the Functions and Macros list, select Digital Operators and Functions. 2 Click the { } entry. 3 In the Simulation Output Variables list, click the signals in high-order to low-order sequence. {Q2,Q1,Q0};A;O specifies a 3bit bus whose most significant bit is Q2. Probe labels the plot A, and values appear in octal notation.
14-28 Digital Simulation Tracking Timing Violations and Hazards not included in: The messaging feature is discussed further in Tracking Digital Simulation Messages on page 17-41 of Chapter 17,Analyzing Waveforms in Probe. When there are problems with your design, such as setup/hold violations, pulse-width violations, or worst-case timing hazards, PSpice A/D logs messages to the simulation output file and/or Probe data file.
Analyzing Results O1 D S Q D ... Q FF1 FF2 C ~Q C ~Q O2 ... O3 e1 e2 Figure 14-2 Circuit with a Timing Error unrelated origins, therefore nothing in common) at the inputs to gate G1, PSpice A/D reports the occurrence as an AMBIGUITY CONVERGENCE hazard. This means that the output of G1 may glitch. Note that the output fans out to two devices, G2 and L1.
14-30 Digital Simulation hazard origin information along with the machine state through all digital devices. When a hazard propagates to a state-storage device primitive (JKFF, DFF, SRFF, DLTCH, RAM), PSpice A/D reports a PERSISTENT HAZARD. Simulation condition messages PSpice A/D produces warning messages in various situations, such as those that originate from the digital CONSTRAINT devices monitoring timing relationships of digital nodes.
Analyzing Results Table 14-4 14-31 Simulation Condition Messages—Timing Violations Message Type Severity Level SETUP WARNING Minimum time required for a data signal to be stable prior to the assertion of a clock was not met. HOLD WARNING Minimum time required for a data signal to be stable after the assertion of a clock was not met.
14-32 Digital Simulation Table 14-5 Simulation Condition Messages—Hazards Message Type Severity Level Meaning AMBIGUITY CONVERGENCE WARNING Convergence of conflicting rising and falling states (timing ambiguities) arrived at the inputs of a primitive and produced a pulse (glitch) on the output. See Chapter 16,Digital Worst-Case Timing Analysis for more information. CUMULATIVE AMBIGUITY WARNING Signal ambiguities are additive, increased by propagation through each level of logic in the circuit.
Analyzing Results 14-33 Output control options Several control options in the Analysis Setup Options dialog box are available for managing the generation of simulation condition messages. These are described in Table 14-6. Table 14-6 Simulation Message Output Control Options Option Meaning NOOUTMSG Suppresses the recording of simulation condition messages in the simulation output file. NOPRBMSG Suppresses the recording of simulation condition messages in the Probe data file.
Mixed Analog/Digital Simulation 15 Chapter Overview This chapter describes how PSpice A/D runs mixed analog/ digital simulations and includes the following sections: Interconnecting Analog and Digital Parts on page 15-1 Interface Subcircuit Selection by PSpice A/D on page 15-3 Specifying Digital Power Supplies on page 15-7 Interface Generation and Node Names on page 15-12 Interconnecting Analog and Digital Parts Prior to simulation, the part instances and nets defined in your schematic are translated into
15-2 Mixed Analog/Digital Simulation netlist. The netlist presents a flat view of the circuit (no hierarchy). Furthermore, PSpice A/D extracts the definitions for all parts modeled as subcircuits, thus viewing parts as a collection of primitive devices and node connections. The digital primitives comprising a given digital part determine the manner in which PSpice A/D processes an analog/digital interface to that part.
Interface Subcircuit Selection by PSpice A/D 15-3 Interface Subcircuit Selection by PSpice A/D AtoD and DtoA interface subcircuits handle the translation between analog voltages/impedances and digital states, or viceversa. The main component of an interface subcircuit is either a PSpice A/D N device (digital input: digital-to-analog) or a PSpice A/D O device (digital output: analog-to-digital). PSpice A/D “N” and “O” devices are neatly packaged into interface subcircuits in the model library .
15-4 Mixed Analog/Digital Simulation Table 15-1 Interface Subcircuit Models Lev el Subcircuits Definition 1 AtoD1/DtoA1 AtoD generates intermediate R, F, and X levels 2 AtoD2/DtoA2 AtoD does not generate intermediate R, F, and X levels 3 AtoD3/DtoA3 (same as level 1) 4 AtoD4/DtoA4 (same as level 2) In the HC/HCT series, we provide two different DtoA models: the simple model and the elaborate model.
Interface Subcircuit Selection by PSpice A/D it provides a more accurate, less optimistic answer. However, this behavior may not be appropriate when the input rise and fall times are long, or when the input voltage never leaves the threshold region. If this is the case, you may want to use the level 2 interface. Level 2 Interface The level 2 AtoD interface transitions directly from 0 to 1 and 1 to 0 without passing through intermediate R, F, or X levels.
15-6 Mixed Analog/Digital Simulation Setting the Default A/D Interface For mixed-signal simulation, you can select the AtoD and DtoA interface level circuit-wide and on individual device instances. • To select the default interface level circuit-wide, select one of the four Default A/D interfaces in the Digital Setup dialog. Part instances whose IO_LEVEL attribute is set to 0 will use this value.
Specifying Digital Power Supplies 15-7 Specifying Digital Power Supplies Digital power supplies are used to power interface subcircuits that are automatically created by PSpice A/D when simulating analog/digital interfaces. They are specified as follows: • PSpice A/D can instantiate them automatically. • You can create your own digital power supplies and place them in the schematic.
15-8 Mixed Analog/Digital Simulation with all primitives appropriately connected to the power supply nodes. Table 15-2 summarizes the default node names and values. For instance, TTL family parts default to 5 volt power supplies at analog/digital interfaces. The default I/O models and power supply subcircuits are found in dig_io.lib. The four default power supplies provided in the model library are DIGIFPWR (TTL), CD4000_PWR (CD4000 series CMOS), ECL_10K_PWR (ECL 10K), and ECL_100K_PWR (ECL 100K).
Specifying Digital Power Supplies 15-9 listed in Table 15-3 in your schematic and redefining the digital power supply nodes. Table 15-3 Digital Power Supply Parts in special.slb Part Type (PSpice A/D “X” Device) Symbol Name CD4000 power supply CD4000_PWR TTL power supply DIGIFPWR ECL 10K power supply ECL_10K_PWR ECL 100K power supply ECL_100K_PWR The attributes relevant to creating custom power supplies are shown in Table 15-4.
15-10 Mixed Analog/Digital Simulation 3 Reset the power supply power and ground voltages as required. 4 For any digital part instance that use the power supply must, set its IPIN attributes to the power and ground node names created by the secondary power supply. Overriding CD4000 power supply voltage throughout a schematic Circuits using CD4000 parts often require power supply voltages other than the default 5.0 volts supplied by the standard CD4000_PWR power supply part.
Specifying Digital Power Supplies Creating a secondary CD4000, TTL, or ECL power supply Circuits using CD4000, TTL, or ECL parts may require power supply voltages in addition to the default 5.0 volts supplied by the standard CD4000_PWR power supply part. To create a secondary power supply for any one of the CD4000, TTL, or ECL technologies, you must place the appropriate power supply part and create user-defined nodes with a new voltage value.
15-12 Mixed Analog/Digital Simulation Interface Generation and Node Names The majority of the interface generation process involves PSpice A/D determining whether analog and digital primitives are connected, and if so, inserting an interface subcircuit for each digital connection. This turns the interface node into a purely analog node, which now connects to the analog terminal of the interface subcircuit.
Interface Generation and Node Names schematic representation PSpice A/D representation Figure 15-1 Mixed Analog/Digital Circuit Before and After Interface Generation node, 2$DtoA, to connect the output of U1 to the digital input of the DtoA interface. The interface subcircuits PSpice A/D automatically generates are listed in the simulation output file under the section named Generated AtoD and DtoA Interfaces.
15-14 Mixed Analog/Digital Simulation **** Generated AtoD and DtoA Interfaces **** * * Analog/Digital interface for node 1 * * Moving X1.U1:.A from analog node 1 to new digital node * 1$AtoD X$1_AtoD1 1 1$AtoD $G_DPWR $G_DGND AtoD_STD + PARAMS: CAPACITANCE= 0 * Moving X2.U1:.A from analog node 1 to new digital node * 1$AtoD2 X$1_AtoD2 1 1$AtoD $G_DPWR $G_DGND AtoD_STD + PARAMS: CAPACITANCE= 0 * * Analog/Digital interface for node 2 * ** Moving X1.U1.
Digital Worst-Case Timing Analysis 16 Chapter Overview This chapter deals with worst-case timing analysis and includes the following sections: Digital Worst-Case Timing on page 16-2 Starting Worst-Case Timing Analysis on page 16-3 Simulator Representation of Timing Ambiguity on page 16-3 Propagation of Timing Ambiguity on page 16-5 Identification of Timing Hazards on page 16-6 Convergence Hazard on page 16-6 Critical Hazard on page 16-7 Cumulative Ambiguity Hazard on page 16-8 Reconvergence Hazard on page
16-2 Digital Worst-Case Timing Analysis not included in: Compared to Analog Worst-Case Analysis Digital worst-case timing simulation is different from analog worst-case analysis in several ways. Analog worst-case analysis is implemented as a sensitivity analysis for each parameter which has a tolerance, followed by a projected worst-case simulation with each parameter set to its minimum or maximum value.
Starting Worst-Case Timing Analysis 16-3 Starting Worst-Case Timing Analysis 1 In the Analysis Setup dialog box, click on the Digital Setup button. Set Timing to Worst-Case (Min/Max, and complete the rest of the Digital Setup dialog box as needed. Click on OK when finished. 2 If needed, in the Analysis Setup dialog box, select ( ✓) the Digital Setup check box to enable it. 3 Start the simulation as described in Starting Simulation on page 8-11.
16-4 Digital Worst-Case Timing Analysis the duration of the timing ambiguity result that represents a primitive’s output change. For example, consider the model of a BUF device in the following figure. U5 BUF $G_DPWR $G_DGND IN1 OUT1 ; BUFFER model + T_BUF IO_STD .
Propagation of Timing Ambiguity Propagation of Timing Ambiguity As signals propagate through the circuit, ambiguity is contributed by each primitive having a nonzero MIN/MAX delay spread. Consider the following example that uses the delay values of the previous BUF model. 35 5 20 85 45 Figure 16-2 Timing Ambiguity Example 2 This accumulation of ambiguity may have adverse effects on proper circuit operation. In the following example, consider ambiguity on the data input to a flip-flop.
16-6 Digital Worst-Case Timing Analysis Identification of Timing Hazards Timing hazard is the term applied to situations in which the response of a device cannot be properly predicted due to uncertainty in the arrival times of signals applied to its inputs. Consider the following signal transitions (0-1, 1-0) being applied to the AND gate.
Critical Hazard This output (0-R-0) should be interpreted as a possible single pulse, no longer than the duration of the R level. The actual device’s output may or may not change, depending on the transition times of the inputs. Note that other types of primitives, such as flip-flops, may produce an X instead of an R-0 or F-1 in response to a convergence hazard. Critical Hazard It is important to note that the glitch so predicted could propagate through the circuit and may cause incorrect operation.
16-8 Digital Worst-Case Timing Analysis Cumulative Ambiguity Hazard In worst-case mode, simple signal propagation through the network will result in a buildup of ambiguity along the paths between synchronization points (see Glitch Suppression Due to Inertial Delay on page 16-12). The cumulative ambiguity is illustrated in Figure 16-8.
Cumulative Ambiguity Hazard Another cause of cumulative ambiguity hazard involves circuits with asynchronous feedback. The simulation of such circuits under worst-case timing constraints yields an overly pessimistic result due to the unbounded accumulation of ambiguity in the feedback path. A simple example of this effect is shown in Figure 16-10.
16-10 Digital Worst-Case Timing Analysis Reconvergence Hazard The simulator recognizes situations where signals having a common origin reconverge on the inputs of a single device (see Figure 16-11). 25 TPLHMN=10 TPLHMX=30 60 U2 D t=0 15 30 U1 Q U4 C U3 TPLHMN=15 TPLHMX=30 TPLHMN=40 TPLHMX=60 55 90 Figure 16-11 Reconvergence Hazard Example 1 The relative timing relationship between the two paths (U2, U3) is the important aspect of this example.
Reconvergence Hazard 16-11 In the event that discounting the common ambiguity does not preclude the X being latched (or, in the case of simple gates, a glitch being predicted), the situation is called a reconvergence hazard. This is nothing more than a convergence hazard with the conflicting signal ambiguities having a common origin.
16-12 Digital Worst-Case Timing Analysis Glitch Suppression Due to Inertial Delay Signal propagation through digital primitives is performed by the simulator subject to constraints such as the primitive’s function, delay parameter values, and the frequency of the applied stimulus. These constraints are applied both in the context of a normal, well-behaved stimulus, and a stimulus that represents timing hazards.
Methodology 16-13 amount of overlap is less than the inertial delay of the device, the prediction of a glitch is also suppressed by the simulator (see Figure 16-15). TPLHMN=40 TPLHMX=60 55 15 90 30 TPLHMN=4 TPLHMX=10 TPLHMN=10 TPLHMX=45 25 75 Figure 16-15 Glitch Suppression Example 3 In this case, the factoring out of the 15 nsec common ambiguity still results in a 5 nsec overlap of conflicting states.
16-14 Digital Worst-Case Timing Analysis Digital worst-case timing simulation does not yield such results without an applied stimulus; it is not a static timing analysis tool. The level of confidence that you establish for your design’s timing-dependent characteristics is directly a function of the applied stimulus.
Methodology For example, in the case of a convergence or reconvergence hazard, look for conflicting rise/fall inputs. In the case of cumulative ambiguity, look for the merging of successive ambiguity regions within two edges forming a pulse.
Part Four Viewing Results Part Four describes the ways to view simulation results. Chapter 17,Analyzing Waveforms in Probe, describes how to perform graphical waveform analysis of simulation results. Chapter 18,Viewing Results on the Schematic, explains how to view bias point voltages, currents, and digital states directly on your schematic to help you quickly debug your circuit.
Analyzing Waveforms in Probe 17 Chapter Overview This chapter describes how to use Probe to perform graphical waveform analysis of simulation results.
17-2 Analyzing Waveforms in Probe Overview of Probe MicroSim Probe is the waveform analyzer for PSpice A/D simulations. In Probe, you can visually analyze and interactively manipulate the waveform data produced by circuit simulation. Probe uses high-resolution graphics so you can view the results of a simulation both on the screen and in hard copy. In effect, Probe is a software oscilloscope.
Overview of Probe Elements of a Probe Plot A single Probe plot consists of the analog (lower) area and the digital (upper) area. digital area analog area Figure 17-1 Analog and Digital Areas of a Probe Plot You can display multiple plots on the screen. If you display only analog waveforms, the entire plot will be an analog area. Likewise, if you display only digital waveforms, the entire plot will be a digital area.
17-4 Analyzing Waveforms in Probe Elements of a Plot Window A plot window is a separately managed waveform display area. A plot window can include multiple analog and digital plots. Figure 17-2 shows the Probe window with two plot windows displayed (toolbars disabled). From the View menu, select Toolbar to display orhide the toolbar. Because a plot window is a window object, you can minimize and maximize the window or move and scale the window within the Probe window area.
Overview of Probe Managing Multiple Plot Windows Any number of plot windows can be opened. Each plot window is an independent window. The same Probe data file can be displayed in more than one plot window. Only one plot window is active at any given time, identified by a highlighted title bar. Menu, keyboard, and cursor operations affect only the active plot window. Another plot window can be made active by clicking anywhere in the window.
17-6 Analyzing Waveforms in Probe Setting Up Probe Configuring Probe Colors You can over-ride the color configuration you set here for traces by assigning colors to markers in Schematics. For more information, see Using Schematic Markers to Add Traces on page 17-13. For information on how to use the available colors and color order in a Probe plot window, see Configuring trace color schemes on page 17-8. Colors for all items are specified as - =.
Setting Up Probe 4 If you added or deleted trace number entries, set NUMTRACECOLORS=n to the new number of traces (1≤n≤12). This item represents the number of trace colors displayed on the screen or printed before the color order repeats. 5 Save the file.
17-8 Analyzing Waveforms in Probe Configuring trace color schemes For information on what the default available colors and color order are and how to change them, see Editing display and print colors in the msim.ini file on page 17-6. Use this option, in conjunction with the Design Journal feature, to see the differences between a working schematic and its checkpoints. See Schematics online Help for more information. Probe saves the selected color scheme for future Probe sessions.
Setting Up Probe 17-9 Customizing the Probe Command Line Command files, .prb files, and options can be specified in the Probe command line. Probe recognizes these options when you start it automatically after simulation or when you start it from Schematics by selecting Run Probe from the Analysis menu. To edit the Probe command line 1 In Schematics, from the Option menu, select Editor Configuration. 2 In the Editor Configuration dialog box, select App Settings.
17-10 Analyzing Waveforms in Probe Running Probe You do not need to quit Probe if you are finished examining the simulation results for one circuit and want to begin a new simulation. However, when you set up Probe to run automatically after simulation, Probe unloads the old data file for a circuit each time that you run a new simulation of the circuit. After the simulation is complete, the new or updated Probe data file is loaded for viewing.
Running Probe 5 6 From the Analysis menu, select Simulate to start the simulation. Probe starts automatically and displays one window in monitor mode. Do one of the following to select the waveforms to be monitored: • In Probe, from the Trace menu, select Add, and enter one or more trace expressions. • In Schematics, from the Markers menu, select and place one or more markers (and marker color, as needed).
17-12 Analyzing Waveforms in Probe Other Ways to Run Probe Starting Probe during a simulation Once a simulation is in progress, you can monitor the results for the data section currently being written by PSpice A/D. This function is only available when Monitor Waveforms (AutoUpdate) is not enabled in Schematics in the Probe Setup Options dialog box. To start Probe during a simulation 1 Start the simulation as described in Starting Simulation on page 8-11.
Running Probe 17-13 Interacting with Probe while in monitor mode All of the Probe functionality is available when in monitor mode. However, functions that change the x-axis domain (set a new x-axis variable) pause monitoring and place the window in manual mode until the x-axis is reverted to its original domain. The following table describes how to enable the functions that change the x-axis domain: Enable this function... By doing this...
17-14 Analyzing Waveforms in Probe • During or after simulation, with Probe running, to automatically display traces in the active plot window. You can also control the color of each marker you place. The color you choose for a marker will also be the color of its trace in Probe. The Markers menu provides additional selections for controlling display of marked results in Probe, after initial marker placement, and during or after simulation.
Running Probe 4 Right-click to quit placing markers. 5 If you have not simulated the circuit yet, from the Analysis menu, select Simulate. To control the display of marked results in Probe 1 In Schematics, from the Markers menu, select one of the following: Choose this option... To do this... Show All Display traces for all markers placed on any page or level of the schematic in Probe.
17-16 Analyzing Waveforms in Probe Limiting file size using markers One reason that Probe data files are large is that, by default, PSpice A/D stores all net voltages and device currents for each step (for example, time or frequency points). However, if you have placed markers on your schematic prior to simulation, PSpice A/D saves only the results for the marked wires and pins. To limit file size using markers 1 In Schematics, from the Analysis menu, select Probe Setup.
Running Probe 17-17 Limiting file size by excluding internal subcircuit data By default, PSpice A/D writes data to the Probe file for all internal nodes and devices in subcircuit models on a schematic. You can choose to exclude data for internal subcircuit nodes and devices. To limit file size by excluding data for internal subcircuits 1 In Schematics, from the Analysis menu, select Probe Setup. 2 In the Probe Setup Options dialog box, select the Data Collection tab.
17-18 Analyzing Waveforms in Probe Using Simulation Data from Multiple Files You can load simulation data from multiple files into the same Probe plot in two ways: You can use the Design Journal feature in Schematics to create checkpoint schematics, which are copies of your working (or current development) schematic at any point of development up to the present. Checkpoint schematics allow you to create an electronic record of design development and to perform what-if analyses on your original schematic.
Running Probe 4 In the Show Results In frame, choose one of the following options: Choose this option... To do this... Same window for all schematics (working and checkpoint) Load the data sets for all open working and checkpoint schematics in one plot window. Separate windows for each working schematic including its checkpoints Load the data sets for each open working schematic and its checkpoints in one plot window.
17-20 Analyzing Waveforms in Probe Adding traces from specific loaded data files If two or more data files have identical simulation output variables, trace expressions that include those variables will plot traces for each file. However, you can specify which data file to use in the trace expression. You can also determine which data file was used to generate a specific trace.
Running Probe 17-21 Figure 17-4 Section Information Message Box Saving Simulation Results in ASCII Format The default Probe data file format is binary. However, you can save the Probe data file in the Common Simulation Data Format (CSDF) instead. To save simulation results in ASCII format 1 In Schematics, from the Analysis menu, select Probe Setup. 2 In the Probe Setup Options dialog box, select the Data Collection tab. 3 Select Text Data File Format (CSDF). 4 Click OK.
17-22 Analyzing Waveforms in Probe Analog Example The example circuit Example.sch is provided with your MicroSim programs. When shipped, Example.sch is set up with multiple analyses. For this example, the AC sweep, DC sweep, Monte Carlo/worstcase, and small-signal transfer function analyses have been disabled. The specification for each of these disabled analyses remains intact.
Analog Example 17-23 PSpice A/D generates a binary Probe data file containing the results of the simulation. The Probe screen displays with the data file, Example.dat, already loaded (Figure 17-6). Figure 17-6 Probe Main Window with Loaded Example.dat and Open Plot Menu The name of the data file, Example.dat, is shown in the title bar. All Probe commands are available through the menu items.
17-24 Analyzing Waveforms in Probe Displaying voltages on nets and currents into pins Having selected an analysis, voltages on nets and currents into device pins can be displayed in the Probe plot using either the schematic marker method or by explicitly specifying Probe output variables (as will be demonstrated in this example). To display the voltages at the OUT1 and OUT2 nets using output variables 1 From the Trace menu, select Add.
Mixed Analog/Digital Tutorial Mixed Analog/Digital Tutorial In this tutorial, you will use PSpice A/D to simulate a simple, mixed analog/digital circuit. You will then use Probe to analyze the output by: • simultaneously displaying analog and digital traces along a common time axis, and • displaying digital data values and features unique to mixed analog/digital circuit analysis, such as identification of digital nets inserted by PSpice A/D.
17-26 Analyzing Waveforms in Probe About the Oscillator Circuit The circuit you will simulate and analyze is a mixed analog/ digital oscillator using Schmitt trigger inverters, an opencollector output inverter, a standard inverter, a JK flip-flop, a resistor, and a capacitor. The schematic is shown in Figure 17-8. Figure 17-8 Mixed Analog/Digital Oscillator Schematic The circuit uses a one-bit digital stimulus device, DSTIM1.
Mixed Analog/Digital Tutorial 17-27 Running the Simulation To run the simulation 1 From the Analysis menu, select Simulate. Because the oscillator circuit used here has been run with only a transient analysis, Probe automatically selects the transient analysis data section from the Probe data file. This means that the Available Selection dialog box is skipped and control is placed immediately into the main Probe window.
17-28 Analyzing Waveforms in Probe Figure 17-9 Voltage at Net 1 with Y-Axis Added To view traces for V(3), RESET, and OUT You can add up to 75 digital traces to the digital portion of the plot. If you add more traces than can be displayed, Probe scrolls the traces upwards so you can see the last trace added. A + character in front of the highest or lowest trace name indicates that there are more traces above or below the marked traces. 1 From the Trace menu, select Add.
Mixed Analog/Digital Tutorial Figure 17-10 Mixed Analog/Digital Oscillator Results 17-29
17-30 Analyzing Waveforms in Probe User Interface Features Probe offers a number of direct manipulation techniques and shortcuts to analyze the waveform data. These techniques are described in this section. Shortcut keys Many of the menu functions in Probe have matching keystrokes. For instance, having placed a selection rectangle in the analog portion of the plot, you can type C+A instead of selecting Area from the View menu. For a list of shortcut keys, from the Help menu, select Keyboard Shortcuts.
User Interface Features 17-31 To zoom in the analog area using the mouse 1 Drag the mouse to make a selection rectangle as shown below. selection rectangle (analog) 2 From the View menu, select Area. Probe changes the plot to display the region within the selection rectangle. The digital portion of the display, if present, is also zoomed. Click anywhere on the plot to remove the selection rectangle without zooming.
17-32 Analyzing Waveforms in Probe Scrolling Traces By default, when a plot is zoomed or when a digital plot contains more traces than can be displayed in the visible area, standard scroll bars appear to the right or at the bottom of the plot area as necessary. These can be used to pan through the data. You can configure scroll bars so they are always present or are never displayed. To configure scroll bars 1 In Probe, from the Tools menu, select Options.
User Interface Features Sizing Digital Plots Sizing bars can be used to change the digital plot size instead of using Digital Size from the Plot menu. The digital trace name sizing bar is at the left vertical boundary of the digital plot. If an analog plot area is displayed simultaneously with the digital plot, there is an additional plot sizing bar at the bottom horizontal boundary of the digital plot.
17-34 Analyzing Waveforms in Probe To set the digital plot size using menu options 1 Display at least one digital trace in the plot for which you want to set the digital size. 2 From the Plot menu, select Digital Size. 3 In the Digital Size dialog box, set the following: 4 For information about adding labels (including text, line, polyline, arrow, box, circle, ellipse, and mark), see the online Help in Probe. • Percentage of Plot to be Digital • Length of Digital Trace Name Click OK.
User Interface Features Moving and Copying Trace Names and Expressions Trace names and expressions can be selected and moved or copied, either within the same plot window or to another plot window. To copy or move trace names and expressions 1 Click one or more (V+click) trace names. Selected trace names are highlighted. 2 From the Edit menu, select Copy or Cut to save the trace names and expressions to the clipboard. Cut removes trace names and traces from the plot window.
17-36 Analyzing Waveforms in Probe For information about adding labels (including text, line, polyline, arrow, box, circle, ellipse, and mark), see the online Help in Probe. Copying and Moving Labels Labels can be selected and moved or copied, either within the same plot window or to another plot window. To copy labels or 1 Select one or more (V+click) labels, or select multiple labels by drawing a selection rectangle. Selected labels are highlighted.
User Interface Features To export the data points to other Windows 95 or NT programs 1 Select one or more (V+click) traces. Selected traces are highlighted. 2 From the Edit menu, select Copy or Cut to save the trace data point values to the Clipboard. Cut will remove traces from the plot window. 3 Paste the data from the Clipboard into the MicroSim Text Editor (or any other text editor), a spreadsheet program, or a technical computing program (such as Mathcad). 4 Save the file.
17-38 Analyzing Waveforms in Probe To move cursors along a trace using menu commands For information about cursors commands, see the online Help in Probe. 1 For a family of curves (such as from a nested DC sweep), you can use the mouse or the arrow keys to move the cursor to one of the other curves in the family. You can also click the desired curve. To move cursors along a trace using the mouse 1 From the Tools menu, point to Cursor, then select Peak, Trough, Slope, Min, Max, Point, or Search.
User Interface Features To move cursors along a trace using the keyboard 1 Use key combinations as described in Table 17-3. Table 17-3 Key Combinations for Cursor Control Key Combination Function C+l and C+r Changes the trace associated with the first cursor. V+C+l and V+C+r Changes the trace associated with the second cursor. l and r Moves the first cursor along the trace. V+l and V+r Moves the second cursor along the trace. h Moves the first cursor to the beginning of the trace.
17-40 Analyzing Waveforms in Probe To position a cursor on the next trough of a waveform, from the Tools menu, point to Cursor, then select Trough. To position a cursor on the next peak of a waveform, from the Tools menu, point to Cursor, then select Peak. For more information about cursors, see the online Help in Probe. Cursor 1 is positioned on the first trough (dip) of the V(1) waveform. Cursor 2 is positioned on the second peak of the same waveform.
Tracking Digital Simulation Messages 17-41 Tracking Digital Simulation Messages Probe provides an interactive message facility that automatically associates errors that occurred during a digital simulation with their corresponding waveforms. You can initiate message analysis from: • the Simulation Message Summary dialog box, or • the waveform display. Message Tracking from the Message Summary A message summary is available for simulations where diagnostics have been logged to the Probe data file.
17-42 Analyzing Waveforms in Probe The Simulation Message Summary dialog box The Simulation Message Summary dialog box lists message header information. You can filter the messages displayed in the list by selecting a severity level from the Minimum Severity Level drop-down menu. Messages are categorized (in decreasing order of severity) as FATAL, SERIOUS, WARNING, or INFO (informational).
Tracking Digital Simulation Messages Figure 17-12 Waveform Display for a PERSISTENT HAZARD Message Message Tracking from the Waveform Trace segments with associated diagnostics are displayed in the foreground color specified in your msim.ini file. This color is different from those used for standard state transitions. To display explanatory message text 1 Double-click within the tagged region of a trace.
17-44 Analyzing Waveforms in Probe Probe Trace Expressions Traces are referred to by Probe output variable names. Probe output variables are similar to the PSpice A/D output variables specified in the Schematics Analysis Setup dialog boxes for noise, Monte Carlo, worst-case, transfer function, and Fourier analyses. However, there are additional alias forms that are valid within Probe. Both forms are discussed here.
Probe Trace Expressions 17-45 Basic Output Variable Form This form is representative of those used for specifying some PSpice A/D analyses.
17-46 Analyzing Waveforms in Probe Output Variable Form for Device Terminals This form can only be specified in Probe. The primary difference between this and the basic form is that the terminal symbol appears before the net or device name specification (whereas the basic form treats this as the pin name within the pin id).
Probe Trace Expressions Table 17-4 Probe Output Variable Formats Format Meaning Voltage Variables V[ac](< +analog net > [,< -analog net >]) Voltage between + and - analog net ids V[ac](< device >) Voltage at pin name of a device V< x >[ac](< 3 or 4-terminal device >) Voltage at nongrounded terminal x of a 3 or 4-terminal device V< z >[ac](< transmission line device >) Voltage at end z of a transmission line device (z is either A or B) Current Variables I[ac](< device >) Current into
17-48 Analyzing Waveforms in Probe Table 17-4 Probe Output Variable Formats (continued) Format Meaning Sweep Variables < DC sweep variable > name of any variable used in the DC sweep analysis FREQUENCY AC analysis sweep variable TIME transient analysis sweep variable Noise Variables V[db](ONOISE) total RMS-summed noise at output net V[db](INOISE) total equivalent noise at input source NTOT(ONOISE) sum of all noise contributors in the circuit N< noise type >(< device name >) contribution f
Probe Trace Expressions Table 17-5 Examples of Probe Output Variable Formats A Basic Form An alias equivalent V(NET3,NET2) (same) voltage between analog nets labeled NET3 and NET2 V(C1:1) V1(C1) voltage at pin1 of capacitor C1 VP(Q2:B) VBP(Q2) phase of voltage at base of bipolar transistor Q2 V(T32:A) VA(T32) voltage at port A of transmission line T32 I(M1:D) ID(M1) current through drain of MOSFET device M1 QA (same) digital state at net QA Meaning {IN1, IN2, IN3}; (same) MYBUS;X di
17-50 Analyzing Waveforms in Probe Table 17-7 Device Names for Two-Terminal Device Types Two-Terminal Device Type* Device Type Letter capacitor C diode D voltage-controlled voltage source** E current-controlled current source** F voltage-controlled current source** G current-controlled voltage source** H independent current source I inductor L resistor R voltage-controlled switch** S independent voltage source V current-controlled switch** W *.
Probe Trace Expressions Table 17-8 Terminal IDs by Three & Four-Terminal Device Type Three & Four-Terminal Device Type Device Type Letter GaAs MESFET B Terminal IDs D (drain) G (gate) S (source) Junction FET J D (drain) G (gate) S (source) MOSFET M D (drain) G (gate) S (source) B (bulk, substrate) Bipolar transistor Q C (collector) B (base) E (emitter) S (substrate) transmission line T A (near side) B (far side) IGBT Z C (collector) G (gate) E (emitter) 17-51
17-52 Analyzing Waveforms in Probe Table 17-9 Noise Types by Device Type Noise Types* Meaning B (GaAsFET) FID RD RG RS SID TOT flicker noise thermal noise associated with RD thermal noise associated with RG thermal noise associated with RS shot noise total noise D (diode) FID RS SID TOT flicker noise thermal noise associated with RS shot noise total noise Digital Input RHI RLO TOT thermal noise associated with RHI thermal noise associated with RLO total noise Digital Output TOT total noise
Probe Trace Expressions Table 17-9 Noise Types by Device Type (continued) Noise Types* Meaning Q (BJT) FIB RB RC RE SIB SIC TOT flicker noise thermal noise associated with RB thermal noise associated with RC thermal noise associated with RE shot noise associated with base current shot noise associated with collector current total noise R (resistor) TOT total noise Iswitch TOT total noise Vswitch TOT total noise Device Type 17-53 *.
17-54 Analyzing Waveforms in Probe Analog Trace Expressions Trace expression aliases Analog trace expressions in Probe vary from the output variables used in PSpice A/D analyses because analog net values can be specified by:
Probe Trace Expressions Table 17-10 Probe Analog Arithmetic Functions (continued) Probe Function Description Available in PSpice A/ D? G(x) group delay of x (seconds) NO PWR(x,y) |x|y YES SIN(x) sin(x) YES COS(x) cos(x) YES TAN(x) tan(x) YES -1 (x) ATAN(x) ARCTAN(x) tan YES d(x) derivative of x with respect to the x-axis variable YES* s(x) integral of x over the range of the x-axis variable YES** AVG(x) running average of x over the range of the x-axis variable NO AVGX(x,d)
17-56 Analyzing Waveforms in Probe Rules for numeric values suffixes Explicit numeric values are entered in the same form as PSpice A/D (by means of symbol attributes in Schematics), with the following exceptions: • Suffixes M and MEG are replaced with m (milli, 1E-3) and M (mega, 1E+6), respectively. • MIL and mil are not supported. Example: V(5) and v(5) are equivalent in Probe.
Probe Trace Expressions 17-57 Digital Trace Expressions Digital output variables in Probe vary from those used in PSpice A/D analyses as follows: For a procedural discussion of digital trace expressions, see • Analyzing Results on page 14-23 in the Digital Simulation chapter. Digital net values are specified by: [;display name] as opposed to the format used by PSpice A/D. With this format, the digital signal can be displayed on the digital plot with an optional alias.
17-58 Analyzing Waveforms in Probe This placeholder... Means this... radix applies only to bus expressions and denotes the radix in which the bus value is to be displayed; the radix is specified as: H or X D O B hexadecimal (default) decimal octal binary Table 17-12 presents the operators available for digital signal and bus expressions listed in order of precedence (high to low).
Probe Trace Expressions 17-59 You can use signal constants in signal expressions. Specify them as shown in Table 17-13. Table 17-13 Probe Signal Constants Signal Constant Meaning ’0 low ’1 high ’F falling ’R rising ’X unknown ’Z high impedance You can use bus constants in bus expressions. Specify them as strings of the form: r'ddd This placeholder... Example notations for bus constants: Means this...
Viewing Results on the Schematic 18 Chapter Overview This chapter describes how to view bias point information directly on your schematic after running a simulation. Viewing Bias Point Voltages and Currents on page 18-2 explains how to use the interactive bias information display feature from the Analysis menu to dynamically show and hide voltages on wire segments and currents on device pins without having to run extra simulations.
18-2 Viewing Results on the Schematic If you used IPROBE and VIEWPOINT symbols in earlier designs... ...you don’t need to anymore. The bias information is always available and saves you steps. Viewing Bias Point Voltages and Currents When using symbols like IPROBE and VIEWPOINT, you typically have to: After simulating, you can display bias point information on your schematic so you can find problem areas in your design.
Viewing Bias Point Voltages and Currents • A given voltage or current source can have a different DC value and initial transient value at TIME=0. This means the initial transient bias calculation can be different from the DC (small-signal) bias point. 18-3 Note For a transient analysis, only the initial transient bias values are available for display. The Bias Information Toolbar Buttons The easiest way to control bias information display is to use the buttons on the simulation toolbar.
18-4 Viewing Results on the Schematic Showing Voltages You can also display the voltage more than once for a net by using the Show/Hide Selected Voltages command on different wire segments. By default, voltage display is initially enabled for all nets in your schematic. This means bias voltage values appear once for each net on each schematic page or level of hierarchy, either under the user-defined label for the net or next to the middle of the longest wire segment.
Viewing Bias Point Voltages and Currents To view a subset of the voltages that are already displayed 1 From the Edit menu, select Select All. 2 From the Analysis menu, point to Display Results on Schematic, and then select Show/Hide Selected Voltages to hide all of the voltage values. 3 Click to deselect everything. 4 Click one or more (shift-click) wire segments or select an area where you want to see voltages on several nets.
18-6 Viewing Results on the Schematic Showing Currents By default, current display is initially disabled for all device pins in your schematic. When you enable current display, the values you see are the currents flowing into the pins. Note For digital parts, current information is not available. To enable/disable current display On the Toolbar 1 this means enabled From the Analysis menu, point to Display Results on Schematic, and then select Enable Current Display.
Viewing Bias Point Voltages and Currents 18-7 Changing the Precision of Displayed Data By default, Schematics displays voltage and current values with four significant digits. This means up to a total of four digits on the left and right of the decimal point. If you want to see more or fewer significant digits, you can change the display setting.
18-8 Viewing Results on the Schematic Note Schematics remembers the position of voltage labels, but not current labels. This means if you close (after having saved changes) and then reopen your schematic, the voltage labels appear where you last positioned them; however, Schematics places each current label at its default location near the corresponding pin. Verifying Label Associations Schematics provides visual cues to help you see what piece of the schematic a voltage or current label describes.
Viewing Bias Point Voltages and Currents 18-9 Changing Display Colors You can change the appearance of the voltage and current labels using Display Preferences in Schematics. Labels are constructed of a frame and text. The frame defines the label’s outline and fill (background) properties. Text defines the color and font of the label’s numeric data.
18-10 Viewing Results on the Schematic If you want obsolete voltage and current labels to change appearance You can also check the title bar in the Schematics window for the word Stale. When you change your schematic, the voltage and current values displayed from a previous simulation may no longer be valid. As a reminder, you can have Schematics change the color of the “stale” voltage and current labels.
Other Ways to View Bias Point Values Other Ways to View Bias Point Values For the analog portion of your circuit, Schematics provides two special symbols to display bias point information: VIEWPOINT and IPROBE. Using the VIEWPOINT Symbol to Display Voltage The VIEWPOINT symbol displays the bias point voltage on a net in your schematic.
18-12 Viewing Results on the Schematic 2 Run the simulation. When the simulation completes, Schematics displays the bias point current next to the IPROBE symbol.
Other Output Options 19 Chapter Overview This chapter describes how to output results in addition to those normally written to the Probe data file or PSpice output file. Viewing Analog Results in the PSpice Window on page 19-2 explains how to monitor the numerical values for voltages or currents on up to three nets in your circuit as the simulation proceeds.
19-2 Other Output Options Viewing Analog Results in the PSpice Window Schematics provides a special WATCH1 symbol that lets you monitor voltage values for up to three nets in your schematic as a DC sweep, AC sweep or transient analysis proceeds. Results display in the PSpice window. To display voltage values in the PSpice window If the results move outside of the specified bounds, PSpice A/D pauses the simulation so that you can investigate the behavior.
Writing Additional Results to the PSpice Output File 19-3 Writing Additional Results to the PSpice Output File Schematics provides special symbols that let you save additional simulation results to the PSpice output file as either line-printer plots or tables. To view the PSpice output file after having run a simulation: 1 From the Analysis menu, select Examine Output.
19-4 Other Output Options If you do not enable a format, PSpice A/D defaults to MAG. 5 6 If you selected the AC analysis type, enable an output format: a Click the attribute name for one of the following output formats: MAG (magnitude), PHASE, REAL, IMAG (imaginary), or DB. b In the Value text box, type any non-blank value. c Repeat the previous steps (a) and (b) for as many AC output formats as you want to see plotted. Repeat steps 2 through 5 for any additional analysis types you want plotted.
Writing Additional Results to the PSpice Output File 4 In the Value text box, type any non-blank value such as Y, YES, or 1. 5 If you selected the AC analysis type, enable an output format. 6 a Click the attribute name for one of the following output formats: MAG (magnitude), PHASE, REAL, IMAG (imaginary), or DB. b In the Value text box, type any non-blank value. c Repeat the previous steps (a) and (b) for as many AC output formats as you want to see tabulated.
19-6 Other Output Options Creating Test Vector Files To find out about vector file syntax, refer to the online MicroSim PSpice A/D Reference Manual. To find out about setting up digital stimuli, see Defining a Schematics provides a special VECTOR symbol that lets you save digital simulation results to a vector file. Whenever any net with an attached VECTOR symbol changes state, PSpice A/D writes a line of time-value data to the vector file using the same format as the file stimulus device.
Setting Initial State A Appendix Overview This appendix includes the following sections: Save and Load Bias Point on page A-2 Setpoints on page A-4 Setting Initial Conditions on page A-6
A- 2 Setting Initial State not included in: If the circuit uses high gain components, or if the circuit’s behavior is nonlinear around the bias point, this feature is not useful. Save and Load Bias Point Save Bias Point and Load Bias Point are used to save and restore bias point calculations in successive PSpice A/D simulations. Saving and restoring bias point calculations can decrease simulation times when large circuits are run multiple times and can aid convergence.
Save and Load Bias Point A-3 Load Bias Point Load bias point is a simulation control function that allows you to set the bias point as an initial condition. A common reason for giving PSpice A/D initial conditions is to select one out of two or more stable operating points (set or reset for a flip-flop, for example). To use load bias point 1 Run a simulation using Save Bias Point for the Analysis Setup dialog box. 2 Prior to running another simulation, click Load Bias Point.
A- 4 Setting Initial State Setpoints Pseudocomponents that specify initial conditions are called setpoints. These apply to the analog portion of your circuit. Figure A-1 Setpoints The example is Figure A-1 includes the following: IC1 a one-pin symbol that allows you to set the initial condition on a net for both smallsignal and transient bias points IC2 a two-pin symbol that allows you to set initial condition between two nets Using IC symbols sets the initial conditions for the bias point only.
Setpoints Unlike the IC pseudocomponents, NODESET provides only an initial guess for some net voltages. It does not clamp those nodes to the specified voltages. However, by providing an initial guess, NODESET symbols may be used to break the tie (in a flip-flop, for instance) and make it come up in a desired state. To guess at the bias point, enter the initial guess in the Value text box for the VALUE attribute. PSpice A/D attaches a voltage source with a 0.
A- 6 Setting Initial State Setting Initial Conditions The IC attribute allows initial conditions to be set on capacitors and inductors. These conditions are applied during all bias point calculations. However, if you select ( ✓) the Skip Initial Transient Solution check box in the Transient Analysis Setup dialog box, the bias point calculation is skipped and the simulation proceeds directly with transient analysis at TIME=0.
Convergence and “Time Step Too Small Errors” B Appendix Overview This appendix discusses common errors and convergence problems in PSpice.
B- 2 Convergence and “Time Step Too Small Errors” Introduction In order to calculate the bias point, DC sweep and transient analysis for analog devices PSpice must solve a set of nonlinear equations which describe the circuit's behavior. This is accomplished by using an iterative technique - the NewtonRaphson algorithm - which starts by having an initial approximation to the solution and iteratively improves it until successive voltages and currents converge to the same result.
Introduction B-3 Each of these can be taken in order. One must keep in mind that PSpice’s algorithms are used in computer hardware that has finite precision and finite dynamic range which produce these limits: • voltages and currents in PSpice are limited to +/-1e10 volts and amps, • derivatives in PSpice are limited to 1e14, and • the arithmetic used in PSpice is double precision and has 15 digits of accuracy. Is There a Solution? The answer is yes for any physically realistic circuit.
B- 4 Convergence and “Time Step Too Small Errors” Are the Equations Continuous? The device equations built into PSpice are continuous. The functions available for behavioral modeling are also continuous (there are several functions, such as int(x), which cannot be added because of this). So, for physically realistic circuits the equations can also be continuous. Exceptions that come are usually from exceeding the limits of the numerics in PSpice.
Introduction Is the Initial Approximation Close Enough? It seems like a Catch-22: Newton-Raphson is guaranteed to converge only if the analysis is started close to the answer. Worse yet, there is no measurement that can tell how close is close enough. PSpice gets around this by making heavy use of continuity. Each analysis starts from a known solution and uses a variable step size to find the next solution. If the next solution does not converge PSpice reduces the step size, falls back and tries again.
B- 6 Convergence and “Time Step Too Small Errors” STEPGMIN An alterative algorithm is GMIN stepping. This is not obtained by default, and is enabled by specifying the circuit analysis option STEPGMIN (either using .OPTION STEPGMIN in the netlist, or by making the appropriate choice from the Analysis/ Setup/Options menu).
Bias Point and DC Sweep B-7 Bias Point and DC Sweep Power supply stepping As previously discussed, PSpice uses a proprietary algorithm which finds a continuous path from zero power supplies levels to 100%. It starts at almost zero (.001%) power supplies levels and works its way back up to the 100% levels. The minimum step size is 1e-6 (.0001%). The first repeating series of the first step starts at zero for all voltages.
B- 8 Convergence and “Time Step Too Small Errors” No leakage resistance A third consideration is to avoid situations which could have an ideal current source pushing current into a reverse-biased p-n junction without a shunt resistance. Since p-n junctions in PSpice have (almost) no leakage resistance and would cause the junction's voltage to go beyond 1e10 volts. The model libraries which are part of PSpice follow these guidelines. Typos can cause unrealistic device parameters.
Bias Point and DC Sweep B-9 Behavioral Modeling Expressions Range limits Voltages and currents in PSpice are limited to the range +/1e10. Care must be taken that the output of expressions fall within this range. This is especially important when one is building an electrical analog of a mechanical, hydraulic or other type of system. Source limits Another consideration is that the controlled sources must turn off when the supplies are almost 0 (.001%).
B-10 Convergence and “Time Step Too Small Errors” Example: A first approximation to an opamp that has an open loop gain of 100,000 is: VOPAMP 3, 5 VALUE = {V(in+,in-)*1e5} This has the undesirable property that there is no limit on the output. A better expression is: VOPAMP 3, 5 VALUE = + {LIMIT(V(in+,in-)*1e5,15v,-15v} where the output is limited to +/- 15 volts. Transient Analysis The transient analysis starts using a known solution - the bias point.
Transient Analysis Skipping the Bias Point The SKIPBP option for the transient analysis skips the bias point calculation. In this case the transient analysis has no known solution to start from and, therefore, is not assured of converging at the first time point. Because of this, its use is not recommended. It inclusion in PSpice is to maintain compatibility with UC Berkeley SPICE. SKIPBP has the same meaning as UIC in Berkeley SPICE. UIC is not needed in order to specify initial conditions.
B-12 Convergence and “Time Step Too Small Errors” Failure at the First Time Step If the transient analysis fails at the first time point then usually there is an unreasonably large capacitor or inductor. Usually this is due to a typographical error. Consider the following capacitor: C 1 3, 0 1Ouf “1O” (has the letter O) should have been “10.” This capacitor has a value of one farad, not 10 microfarads. An easy way to catch these is to use the LIST option (on the .OPTIONS command).
Transient Analysis Parasitic Capacitances It is important that switching times be nonzero. This is assured if devices have parasitic capacitances. The semiconductor model libraries in PSpice have such capacitances. If switches and/or controlled sources are used, then care should be taken to assure that no sections of circuitry can try to switch in zero time.
B-14 Convergence and “Time Step Too Small Errors” The parallel resistor gives a good model for eddy current loss and limits the bandwidth of the inductor. The size of resistor should be set to be equal to the inductor's impedance at the frequency at which its Q begins to roll off. Example: A common one millihenry iron core inductor begins to roll off at no less than 100KHz. A good resistor value to use in parallel is then R = 2*π*100e3*.001 = 628 ohms.
Diagnostics B-15 Diagnostics If PSpice encounters a convergence problem it inserts into the output file a message that looks like the following. ERROR -- Convergence problem in transient analysis at Time = Time step = 47.69E-15, minimum allowable step size = 7.920E-03 300.0E-15 These voltages failed to converge: V(x2.23) V(x2.25) = = 1230.23 / -68.4137 -1211.94 / 86.6888 These supply currents failed to converge: I(X2.L1) I(X2.L2) = = -36.6259 / 2.25682 -36.5838 / 2.
B-16 Convergence and “Time Step Too Small Errors” The Last node voltages tried... trailer shows the voltages tried at the last Newton-Raphson iteration. If any of the nodes have unreasonable large values this is a clue that these nodes are related to the problem. “These voltages failed to converge” lists the specific nodes which did not settle onto consistent values. It also shows their values for the last two iterations.
Index A ABM ABM part templates, 6-6 abm.
Index-2 IGBT, 4-12, 8-9, 17-51 inductors, 8-8 integrators and differentiators (ABM), 6-7, 6-14 JFET, 4-12, 8-9, 17-51, 17-52 Laplace transform (ABM), 6-8, 6-18, 6-28, 6- 35, 6-41 limiters (ABM), 6-7, 6-10 math functions (ABM), 6-8, 6-21 mathematical expressions (ABM), 6-28 MOSFET, 4-12, 8-9, 17-51, 17-52 nonlinear magnetic core, 4-12 opamp, 4-12 passive, 3-11 PSpice A/D-equivalent parts (ABM), 6-28 resistors, 8-8, 17-53 switch, 17-53 table look-up (ABM), 6-7, 6-14, 6-28, 6-33 transmission lines, 8-9, 17-51
Index-3 approximations, B-5 behavioral modeling expressions, B-9 bias point, B-7 bipolar transistors, B-14 continuous equations, B-4 DC sweep, B-7 derivatives, B-4 diagnostics, B-15 dynamic range of time, B-11 inductors and transformers, B-13 Newton-Raphson requirements, B-2 parasitic capacitances, B-13 semiconductors, B-7 switches, B-8 transient analysis, B-10 Create Subcircuit command, 4-7, 4-37 current source, controlled, 6-28, 6-46 cursors, Probe, 17-37 custom symbol creation for models, 5-13 using the
Index-4 DRVL (I/O model parameter), 15-13 DRVL (I/O model), 7-18, 7-22 DRVZ (I/O model), 7-18 DtoA interface, see mixed analog/digital circuits dynamic range of time, B-11 E ECL_100K_PWR digital power symbol, 3-22 ECL_10K_PWR digital power symbol, 3-22 EGND ground symbol, 3-32 examples and tutorials AC sweep, 10-6 AC sweep analysis, 2-20 bias point detail analysis, 2-6 creating a digital model, 7-37 DC sweep analysis, 2-10 example circuit creation, 2-2 frequency response vs.
Index-5 IF_IN interface port symbol, 3-26, 14-5, 14-6 IGBT, 4-12, 8-9, 17-51 imaginary part, 17-49 include files, 1-12 configuring, 1-14, 4-41 with model definitions, 4-43 inductors, 8-8 problems, B-13 inertial delay, 7-15 initial conditions, A-2, A-6 INLD (I/O model), 7-18 input noise, total, 10-12 INR (I/O model), 7-18 instance models changing model references, 4-38 editing, 4-22 model editor, 4-33 Parts utility, 4-20 reusing, 4-39 saving for global use instead using the model editor, 4-34 using the Parts
Index-6 schematic editor, 4-33 symbol editor, 4-31 model libraries, 1-12, 4-4 adding to the configuration, 4-44 analog list of, 3-29 and duplicate model names, 4-43 configuration, 4-5 configured as include files, 4-43 configuring, 1-14, 3-30, 4-41 digital list of, 3-29 directory search path, 4-46 global vs.
Index-7 DIGMNTYMX, 16-3 DIGMNTYSCALE, 7-12 DIGOVRDRV, 7-23 DIGTYMXSCALE, 7-12 NOOUTMSG, 14-33 NOPRBMSG, 14-33 RELTOL, 6-45 origin, symbol, 5-16 OUTLD (I/O model), 7-18 output control symbols, 3-7, 19-3 output file (.
Index-8 multiple Y axes, 12-6, 17-27 output variables, 17-44, 17-57 for noise, 10-12, 17-52 performance analysis, 2-30, 12-3 placing a cursor on a trace, 2-13 plot, 17-3 plot update methods, 17-34 plot windows, 17-4 printing plot windows, 17-5 scrolling, 17-32 shortcut keys, 17-30 sizing plots, 17-33 startup, 17-10 trace data tables, 17-36 traces, 17-15 traces, displaying, 2-11, 17-30 traces, using output variables, 17-44 using markers, 17-13 waveform families, 2-27, 9-7 zoom regions, 17-30 propagation dela
Index-9 DC sweep, 9-5 for multiple analysis types, 3-25 loops (digital), 14-14 signal transitions (digital), 14-9 transient (analog/mixed-signal), 11-3 transient (digital), 14-5 subcircuits, 4-3 analog/digital interface, 15-1 creating .
Index-10 VIEWPOINT (bias point voltage display), 18-11 VPULSE (transient stimulus), 3-23 VPWL (transient stimulus), 3-23 VPWL_F_N_TIMES (transient stimulus), 3-24 VPWL_F_RE_FOREVER (transient stimulus), 3- 23 VPWL_N_TIMES (transient stimulus), 3-24 VPWL_RE_FOREVER (transient stimulus), 3-23 VSFFM (transient stimulus), 3-24 VSIN (transient stimulus), 3-24 VSRC (analog stimulus), 3-21, 3-23, 3-26, 9-5, 10-3 VSTIM (analog stimulus), 3-23 VSTIM (transient stimulus), 3-24 WBREAK (current-controlled switch), 3-
Index-11 switching times (TSW), 7-11 transport delay, 7-16 unspecified timing constraints, 7-13 timing violations and hazards convergence, 14-32 cumulative ambiguity, 14-32 persistent hazards, 14-28 total noise, 10-10 circuit, 10-12 per device, 10-12 TPWRT (I/O model), 7-15, 7-18 traces adding, 2-11 direct manipulation, 17-30 displaying, 2-11, 2-18 markers, 17-15 output variables, 17-44 placing a cursor on, 2-13 transformer problems, B-13 transient analysis, 8-2 example, 2-16 Fourier analysis, 8-2 hysteresi
Index-12 waveform reports, 13-4 with temperature analysis, 13-6 Z zoom regions, Probe, 17-30
