Technical data

CHALLENGE/Onyx Diagnostic Road Map 5-1

Chapter 5

5. PROM Monitor

5.1 Overview

This Chapter describes the power-on tests, describes how the Everest boards are

conﬁgured, and explains the Monitor boot commands.

5.2 Power-On Tests

The power-on tests are initiated when the System Controller sends the SCLR signal,

resetting the processors. This series of tests begins with the CPU logic supporting each

individual processor and expands to test and conﬁgure the entire system. Although the

sequences for the IP19 and IP21 are similar, there are differences in the order and type of

power-on tests.

Section 5.2.1 describes the IP19 power-on tests, and Section 5.2.2 describes the IP21

power-on tests.

5.2.1 IP19 Power-On Tests

The power-on test sequence for the IP19 CPU board is illustrated in the ﬂowchart that

spans Figure 5-1 through Figure 5-4.