Technical data

ix
Figures
Figure 1-1 Everest Functional Block Diagram......................................................... 1-2
Figure 1-2 IO4 Functional Block Diagram................................................................1-3
Figure 1-3 Everest System Buses ...............................................................................1-6
Figure 1-4 Everest Buses and Interface ASICs.........................................................1-7
Figure 1-5 Polled Serial Bus........................................................................................1-8
Figure 1-6 SCSI Drive Addressing ............................................................................1-9
Figure 2-1 Everest Bus Parity Checkpoints..............................................................2-7
Figure 2-2 IP19 Board Error Detection Logic...........................................................2-8
Figure 2-3 IP19 Board Component Locations..........................................................2-9
Figure 2-4 IP21 Board Error Detection Logic.........................................................2-12
Figure 2-5 IP21 Board Component Placement.......................................................2-13
Figure 2-6 IO4/VCAM Board Error Detection Logic...........................................2-18
Figure 2-7 IO4/VCAM Component Locations......................................................2-19
Figure 2-8 MC3 Memory Board Error Detection Logic........................................2-25
Figure 2-9 MC3 Board Component Locations.......................................................2-26
Figure 2-10 MC3 SIMM Bank and Leaf Organization............................................2-26
Figure 3-1 Power Subsystem Block Diagram...........................................................3-2
Figure 3-2 Rackmount and Deskside Status Panel and OLS Power and
Fault Indicators..........................................................................................3-4
Figure 3-3 IP19 and IP21 Board Power Fault Indicators and Power Brick
Locations ....................................................................................................3-5
Figure 3-4 MC3 Board Fault Indicator and Power Brick Locations .....................3-6
Figure 3-5 First IO4 Board/VCAM Fault Indicator and Voltage Regulator
Locations .................................................................................................... 3-7
Figure 3-6 Remote VCAM Fault Indicator and Voltage Regulator
Locations ....................................................................................................3-8
Figure 3-7 F Mezzanine Board Fault Indicator and Voltage Regulator
Locations ....................................................................................................3-9
Figure 3-8 Power Board Fault LEDs..........................................................................3-9
Figure 3-9 SCSIBox Fault Indicators .......................................................................3-10
Figure 3-10 Power OK (POKx) Signals.....................................................................3-11
Figure 3-11 Power-On Sequence (Part 1 of 2)..........................................................3-12
Figure 3-12 Power-On Sequence (Part 2 of 2)..........................................................3-13
Figure 3-13 Power-On Signal Timing.......................................................................3-14
Figure 3-14 System Controller Voltage Status Menu..............................................3-14