Technical data

3-2 Power Subsystem
Figure 3-1 Power Subsystem Block Diagram
OLS 1
PFW
RI_L
OLS 2
PFW
RI_L
OLS 3
PFW
RI_L
PFWA
RIA
PFWB
RIB
PFWC
RIC
L & XL Chassis
XL Chassis
XL w/CC3
First SCSI Box
SCSIbox 2 w/512S
XL Chassis only
BLOA,B_TACH
BLOA,B_MTR
SENSE V5 1
POKA
PENA,B
SENSE V12 1
PARA
All chassis:
512 power
board
SENSE V5 1,2
POKA
PENA,B
PARA
XL chassis:
dual−505
(505x2)
boards
SENSE V5 1,2
POKA
PENA,B
PARA
L chassis and XL
Cardcage 3:
505 power
boards
48 VDC − 1.5 VDC
EBus
12V
LOC
5V
AUX
SERIAL_CLK, SERIAL_BRDIN, SERIAL_ADDR<5..0>
SERIAL_CLK, SERIAL_BRDIN, SERIAL_ADDR<5..0>
EXT_SERIAL_, CTS, DCD, SERIAL_BRDOUT
PENA, B, C, D, E: RIA, B, C; BLOA,B_MTR
EXT_SERIAL_SEND, RTS, DTR
PENE, POKE for external peripherals; XRx, XT
x
OVERTMP
PENA,B
POKA,B
First IO4
GE10
MC3
PENB, POKB
via IO4, VCAM
System
Controller
MEZ
MEZ
VCAM
OVERTMP
PENA,B
POKA,B
OVERTMP
PENA,B
POKA,B