Technical data

2-16 Diagnostic Procedures
was prevented from
sending to the EBus by
some other board.
+ 5:Addr Error on MyReq on EBus Channel 0
+ 6:Addr Error on MyReq on EBus Wback Channel
7 If bit 2 is also
asserted (A Chip Addr
Parity), then the error
came in from the EBUS.
Look for error
indicators on other
boards to find the
source of the error.
+ 7:Data Sent Error Channel 0 5,6
+ 8:Data Sent Error Wback Channel
5,6 If this bit is asserted
without DB error (bits 0
or 1)then the error is
in the path between D
chip and DB chip.
If this bit is asserted
with DB error, then the
error is in the path
between the indicated DB
chip and the FPU.
+ 9:Data Receive Error 2 This bit is reliable
when on, unreliable when
off. Indicates that data
with an error was
received from the EBUS.
Interrogate error
indicators on other
boards to identify the
source of the error.
In particular, you may
see DB errors for other boards.
If there are no DB errors for
other boards, there may be a
problem with the IO4, memory,
or the IP21 processor itself.
+ 10:Intern Bus vs. A_SYNC10 7 The CC chip and A chip
both monitor the state
of the EBUS. This bit
set indicates that they
disagree on what state
the bus is in. Indicates
an error in the either
the CC or the A chip.
+ 11: A Chip MyResponse Data Resources Timed Out
7 Timed out on the A-chip.
Read request made it to