Technical data

2-14 Diagnostic Procedures
IP21 Board Error Messages
HARDWARE ERROR STATE:
IP21 in slot 1
+ A Chip Error Register: 0xffff
+ 0:CPU 0 CC->A Channel 0 parity error
+ 1
+ 1:CPU 0 CC->A Wback Channel parity error
+ 1
+ 2:CPU 1 CC->A Channel 0 parity error
+ 1
+ 3:CPU 1 CC->A Wback Channel parity error
+ 1 Error in the path between the
indicated CC Chip and the
A chip.
+ 4:ADDR_ERROR on EBUS 2 This A Chip detected an
address emitted by some
board on the EBUS with
bad parity.
+ 5:My ADDR_ERROR on EBUS 2 Some board detected a parity
error on an address emitted by
this A Chip.
+ 12:CPU 0 ADDR_HERE not asserted 2
+ 13:CPU 0 ADDR_HERE not asserted 2
+ 14:CPU 1 ADDR_HERE not asserted 2
+ 15:CPU 1 ADDR_HERE not asserted 2 A Chip emitted an address that
was not decoded by any board.
+ CC in IP21 Slot 1, cpu 0
+ CC ERTOIP Register: 0xffff
+ 0:DB chip Parity error DB0 5
+ 1:DB chip Parity error DB1 6 Need to examine other error
bits in the ERTOIP register
to determine the cause of
the problem.
If bit 7 (Data Sent
Error Channel 0) is set,
then an error occurred
between the FPU and the
DB Chip.
If bit 8 (Data Sent
Error, Wback Channel) is
set an error occurred
during the write-back of
a dirty cache line
between the Gcache and
the DB chip.
If bit 9 (Data Receive
Error) is set, it may
indicate that the data
received from the EBUS
had a parity error. It
can also indicate a
problem with one of the