Technical data

2-12 Diagnostic Procedures
Figure 2-4 IP21 Board Error Detection Logic
Addr/Cmd (48 + 2 Parity)
Data (256 + 8 Parity)
D
ASIC
D
ASIC
A
ASIC
D
ASIC
D
ASIC
3
21
5
4
DBO
6
DB1
DBO
DB1
Channel 0 17+P
wb Channel 17+P
128+p
256+p
CC
Cmd 7
GCache
FPU
7
Bus
Tag
IU
Processor Tags
Tbus
Idb
128+p
CC
GCache
FPU
Bus
Ta g
IU
Processor Tags
Tbus
ldb
128+p
sdb 128+p
sdb: stor data bus
ldb: load data bus
wb channel: write back channel
A_ADDR