Technical data

2-6 Diagnostic Procedures
A difficult fault to trace is one that occurs in an IP19-based system during a memory write.
If an IP19 issues a memory or PIO write, and an error occurs, an error interrupt is sent to
one of the CPUs. The CPU receiving the interrupt may not be the same CPU that issued the
write operation. The difficulty is compounded when the error occurred during a
transaction that originated in a DMA controller.
The Ebus is highly pipelined, and an operation, once initiated, may not be completed until
some time later. Understanding these asynchronous operations requires understanding the
ways errors propagate through the hardware. In the Everest board set, all interfaces are
bridged by one or more ASICs. By associating specific error bits with a particular ASIC, and
by establishing the direction of information transfer within an interface, the error can
generally be traced back to its point of origin (or to an FRU level).
The figures in the following sections provide the locations of the error-checking logic for
each board, as well as the direction in which the information is flowing when checked. The
boards described are:
• IP19
• IP21
•MC3
• IO4/VCAM
Figure 2-1 provides an overview of the points in the system where errors are detected.
Figure 2-2 through Figure 2-9 illustrate parity checking on each board. The error registers
for each board are also described.