Technical data

6-42 Interactive Diagnostics Environment (IDE)
cstate11 (WMH_DE_DE) Write miss primary (DE) and hit secondary (DE).
cstate12 (RMM_I_I) Read miss primary (I) and secondary (I). Check
that value is correct, that secondary and memory
still have old value and that both lines are CE.
cstate13 (RMM_I_CE) Read miss primary (I) and miss secondary (CE).
Check that value is correct, that secondary and
memory still have old value and that both lines
are CE.
cstate14 (RMM_I_DE) Read miss primary (I) and miss secondary (DE).
Check that secondary line matches memory, that
both tags are CE, that the addr tags on both lines
are correct, and that the dirty altaddr secondary
line was flushed to memory.
cstate15 (RMM_CE_CE) Read miss primary (CE) and miss secondary
(CE). Fill cache lines with a word from
physaddr+secondarycachesize; do a read, then
check that the tags for both lines are CE and have
the correct phys addrs, and that the alternate
memory word hasn’t changed ###.
cstate16 (RMM_DE_DE) Read miss primary (DE) and miss secondary
(DE). Fill cache lines with a word from
physaddr+secondarycachesize; do a read, then
check that the tags for both lines are now CE and
have the correct phys addrs, and that the
alternate memory word was written when the
altaddr line was flushed.
cstate17 (WMM_I_I) Write miss primary (I) and secondary (I). Check
that secondary line matches memory, that both
tags are DE, and that the addr tags on both lines
are correct.
cstate18 (WMM_I_CE) Write miss primary (I) and miss secondary (CE).
Check that secondary line matches memory, that
both tags are DE, and that the addr tags on both
lines are correct.
Cache State Transition Test Description
Table 6-8 Cache State Transition Tests