Technical data

6-38 Interactive Diagnostics Environment (IDE)
cache42 (sd_hitwbinv) - Secondary Hit Writeback Invalidate Test
This verifies the hit writeback invalidate cache operation. It verifies that the data can be
written back from the secondary or in the case where the primary data is more current, that
the data is written from the primary to memory. Also checked is that the cache lines are
invalidated.
Possible errors:
010506e: Initialization error, unexpected Cache write through to memory
addr = %x
expected = %x, actual = %x, XOR %x
Seconday TAG %x
010506f: S-Cache TAG error after Hit Writeback Invalidate cacheop
0105070: Data not written back from Scache to Memory after Hit Writeback
Invalidate Cacheop
addr = %x
expected = %x, actual = %x, XOR %x
Seconday TAG %x
0105071: Initialization error, unexpected Cache write through to memory
addr = %x
expected = %x, actual = %x, XOR %x
Seconday TAG %x
0105072: S-Cache TAG error after Hit Writeback Invalidate cacheop, test case 2
0105073: Error in Primary Cache TAG after a Hit Writeback Invalidate cacheop on
the SCache
addr %x
Expected cache state: Invalid
Primary Data TAG %x
0105074: Data not written back from D-Cache to Memory on a Hit Writeback
Invalidate on the S-Cache
addr = %x
expected = %x, actual = %x, XOR %x
Seconday TAG %x
Primary Data TAG %x
For errors 010506f and 0105072, the following additional information is provided:
Error in Secondary Cache TAG State field
OR Error in Secondary Cache TAG physical tag field
OR Error in Secondary Cache TAG Virtual Address field
Address 0x%08x\nSecondary TAG Data 0x%08x
Expected Cache State: 0x%x = [STATE]
STATE is one of the decoded cache states: Invalid, Clean Exclusive, Dirty Exclusive, Shared,
and Dirty Shared.