Technical data

6-32 Interactive Diagnostics Environment (IDE)
cache30 (i_hitwb) - Primary Instruction Hit Writeback Test
This tests the Hit Writeback cache operation on the instruction cache.
Possible errors:
0104047: I-cache state error during initialization
Cache state did not change to valid when filled from memory
Cache line address: 0x%08x
Expected cache state: 0x%08x Actual cache state: 0x%08x
0104048: I-cache state error Hit writeback happened on a cache miss
Cache line address: 0x%08x
Miss address: 0x%08x
0104049: I-cache Hit writeback did not happen on a cache hit
Cache line address: 0x%08x
expected %x, actual %x, XOR %x
cache31 (ECC_reg_tst) - ECC Register Test
This tests the data integrity of the ECC register. Sliding one and sliding zero patterns are
used in this test.
Possible errors:
010404a: ECC register failed walking one test
Expected data: 0x%08x Actual data: 0x%08x
010404b: ECC register failed walking zero test
Expected data: 0x%08x Actual data: 0x%08x
cache32 (dd_hitinv) - Primary Data Hit Invalidate Test
This tests the Hit Invalidate cache operation on the data cache.
Possible errors:
010404c: D-cache state error during initialization
Cache state did not change to valid when filled from memory
Cache line address: 0x%08x
Expected cache state: 0x%08x Actual cache state: 0x%08x
010404d: D-cache state error
Hit Invalidate changed the line to invalid on a miss
Cache line address: 0x%08x
Miss address: 0x%08x
Expected cache state: 0x%08x Actual cache state: 0x%08x
010404e: D-cache state error on a Hit Invalidate Cache OP
Hit Invalidate did not invalidate the line on a hit
Cache line address: 0x%08x
Expected cache state: 0x%08x Actual cache state: 0x%08x