Technical data

6-26 Interactive Diagnostics Environment (IDE)
cache12 (d_tagparity) - Primary Data TAG RAM Parity Test
This tests the functionality of the parity bit in the primary data cache tag. For each tag, a
stream of ones and zeros are shifted into the tag to check if the parity bit change state
accordingly.
Possible error:
0104018: D-cache tag ram parity bit error
Tag ram address: 0x%08x expected content: 0x%08x
Taglo: 0x%08x expected parity: 0x%x actual parity: 0x%x
cache13 (d_tagcmp) - Primary Data TAG Comparator Test
This tests the comparator at the D-cache tag for hit and miss detection. For each tag, it sets
the ptag field with the values that will cause a cache hit for the Kseg0 address of 0x80002000
to 0x9fffffff. The values used are a walking-one or a walking-zero pattern. This ensure only
one bit location is tested at the comparator. The cache operation Hit Invalidate is used to
check for cache hit and miss situations.
Possible errors:
0104019: D-cache tag comparator did not detect a miss
0104020: D-cache tag comparator did not detect a hit
For each of the above errors, the following additional information is provided:
Tag ram address: 0x%08x
PTag field of tag: 0x%06x comparing with PFN: 0x%06x
cache14 (d_tagfunct) - Primary Data TAG Functionality Test
This tests the functionality of the data cache tag. Kseg0 addresses are used to load the cache
from memory. The ptag and the cache state field are checked to see if they are holding
expected values. Virtual addresses 0x80000000, 0x80002000, 0x80004000, 0x80008000, ...
0x90000000 are used as the base address of an 8k page which is mapped to the cache. The
ptag and state of each cache line are checked against the expected value.