Technical data

CHALLENGE/Onyx Diagnostic Road Map 6-23
6.4.4 Cache Tests
There are forty-eight tests to check the primary and secondary cache of the MIPS
R4000/R4400. They are described in the following sections.
cache1 (Taghitst) - TagHi Register Test
This tests the data integrity of the TagHi register. A sliding-one and a sliding-zero pattern
are used.
Possible errors:
0104001: Taghi register failed walking one test
Expected data: 0x%08x Actual data: 0x%08x
0104002: Taghi register failed walking zero test
Expected data: 0x%08x Actual data: 0x%08x
cache2 (Taglotst) - TagLo Register Test
This tests the data integrity of the TagLo register. A sliding-one and a sliding-zero pattern
are used.
Possible errors:
0104003: Taglo register failed walking one test
Expected data: 0x%08x Actual data: 0x%08x
0104004: Taglo register failed walking zero test
Expected data: 0x%08x Actual data: 0x%08x
cache3 (pdtagwlk) - Primary Data TAG RAM Data Line Test
This checks the data integrity of the primary data TAG RAM path using walking-ones and
walking-zeros patterns.
Possible error:
0104005: D-cache tag ram data line error
Failed walking one (or zero) test at 0x%08x
Expected: 0x%08x Actual 0x%08x
cache4 (pdtagadr) - Primary Data TAG RAM Address Line Test
This tests the address lines to the primary data cache TAG RAM by sliding a one and then
a zero on the address lines. This test assumes that the TagLo register is in good working
condition, and therefore you should run the cache2 (Taglotst) test before this one.
Possible error:
0104006: D-cache tag ram address line error
Failed walking one (or zero) test at 0x%08x
Expected: 0x%08x Actual 0x%08x