Technical data

6-18 Interactive Diagnostics Environment (IDE)
tlb4 (tlb_valid) - Check TLB Valid Exception
Tests to see if TLB invalid accesses generate exceptions. Maps the TLB entries to invalid
addresses in k2seg and attempts to access them.
Possible errors:
0108016: TLB entry %d invalid exception VADDR error : Expected 0x%x Got 0x%x
0108017: TLB entry %d invalid exception didn’t occur
tlb5 (tlb_mod) - Check TLB Modification Exception
This test sets up the TLB to map each page as nonwritable, then attempts to write to each
of the mapped pages. It verifies that an exception is generated for each write attempt.
Possible errors:
010800b: TLB %s entry %d mod exception VADDR error : Expected 0x%x Got 0x%x
010800c: TLB %s entry %d mod exception didn’t occur
010800d: TLB %s entry %d unexpected exception during mod
010800e: TLB %s entry %d mod error : Wrote 0x%x Read 0x%x
tlb6 (tlb_pid) - Check TLB Refill Exception
Tests each TLB slot by attempting access with both matching and nonmatching process id.
It verifies that matching PID accesses are allowed and nonmatching PID accesses generate
exceptions.
Possible errors:
0108015: TLB %s entry %d unexpected exception with matching pid 0x%x
0108016: TLB %s entry %d refill exception VADDR error : Expected 0x%x Got 0x%x
0108017: TLB %s entry %d refill exception didn’t occur
tlb7 (tlb_g) - Check Global Bit In TLB Entry
Sets up all the TLB slots to allow global access, then attempts access on all slots with a
variety of different PID settings. This test passes only if no invalid access exceptions occur.
Possible error:
010801d: Unexpected exception occurred during global access