Technical data

CHALLENGE/Onyx Diagnostic Road Map 6-9
6.3.4 Everest Peripheral Controller (EPC)
Table 6-5 lists tests for the Everest peripheral controller (EPC) on the IO 4 board
Test Function Description
epc_regtest Read/write test for EPC chip
registers.
Performs basic read/write
tests on EPC chip registers,
including the parallel port
registers. Tests the following
registers:
EPC_IIDDUART0
EPC_IIDDUART1
EPC_IIDENET
EPC_IIDPROFTIM
EPC_IIDSPARE
EPC_IIDPPORT
EPC_IIDERROR
EPC_EADDR[0-5]
EPC_TCMD
EPC_RCMD
EPC_TBASELO
EPC_TBASEHI
EPC_TLIMIT
EPC_TTOP
EPC_TITIMER
EPC_RBASELO
EPC_RBASEHI
EPC_RLIMIT
EPC_RTOP
EPC_RITIMER
EPC_PPBASELO
EPC_PPBASEHI
EPC_PPLEN
EPC_PPCTRL
This is a good basic test for the
parallel port. For a more
thorough testing a test fixture
is required.
epc_nvram Read/write test for EPC
NVRAM
Performs a read/write pattern
and address-in-address
testing for all the NVRAM
accessible to the EPC chip.
Although the NVRAM is
physically on the real-time
clock (RTC) chip, it occupies a
separate address space and is
accessed differently, and thus
requires a separate test.
Table 6-5 Everest Peripheral Controller (EPC) Tests