Technical data

5-4 PROM Monitor
Figure 5-3 Power-On Test Sequence (Part 3 of 4)
Configure
console port
Test
main IO4
Configure cache
as stack - jump to
C code
2
Pass
Display message
on System
Controller - stop
Fail
Check main
EPC
Configure
IO4s
Pass
Display message
on System
Controller - stop
Fail
Check EPC
UART
Read
NVRAM
Pass
Display message
on System
Controller - continue
Fail
Check NVRAM
for things to disable
Are we
disabled?
Yes
Jump to
bootmaster
arbitration
Test raw memory
and store results*
Configure
memory
Test configured memory
and store results
Test PROM
memory
3
No
Pass
Fail