Specifications

o or 1
READ
STATUS
,
v
,
.,
A/D
A/D
TIMER
TIMER
INT INT
DONE
OVERRUN
2 1
8 4
2 1
-...,.
MUX
ADDRESS
CURRENTLY
IN
A/O
2 or 3
4
or
S
O.
7.
8.
9.
At
B
C or D
E or F
LOW
8
BITS
OF
A/D
READING
THIS
PORT
WILL
CAUSE
THE
CPU
TO
WAIT
FOR
END
OF
CONVERSION
IN
THE
READY
LINE
SWITCH
(SW3-6)
IS
IN
AND
THE
WAIT
BIT
IS
SET.
HIGH
8
BITS
OF
A/D
or
16
BITS
OF
A/D
READING
THIS
PORT
WILL
RESET
THE
DONE
BIT
AUTOMATICALLY.
IF
THE
OVERRUN
BIT
IS
USED
THEN
THIS
PORT
MUST
ALWAYS
BE
READ
AFTER
PORT
2
ARE
NOT
USED
DATA
PORT
OF
AM9513
COMMAND
PORT
OF
AM9513
REGISTER
ASSIGNMENTS
~
~