Specifications
16
6.
The
Status Register
An
eight
bit
status
register
;s
available for interogation
by
the
CPU
at
any
time.
(See
Register Assignments·
READ)
The
four
bits
of the channel counter ;n the
AID
module
form
the lower
bits
of the
status
register.
8VERRUN
and
DONE
flip-flops
may
be
read in
bits
6
and
7,
respective"j.
Timer
interrupt
flip-flops
1
and
2
may
be
read
in
bits
4 and 5.
The
timer
flip-flops
are
described
;n
the
interrupt
section.
7.
Interrupts
The
AD212
can
provide
either
polled or vectored
interrupts
from
any
combination
of
four sources.
These
sources are
OVERRUN.
DONE.
and
timer
interrupts
1
and
2.
The
ability
of
a given source
to generate
an
interrupt
may
be
enabled
or
disabled
by
setting
or
clearing. respectively. the corresponding
bit
in the
command
register.
For
polled
interrupts.
the
state
of
each
source
may
be
examined
by
the
CPU
in the upper four
bits
of
the
status
register.
Vectored
interrupts
are enabled
by
soldering wires
from
the desired source pins to the desired vector
priority
level
pins
VIO
through
VI7
on
the vectored
interrupt
header.
Any
combination of connections
is
allowed herei
ie
.•
each source
may
go
to a
different
vector
priority
level.
or
at
the other extreme,
all
sources
may
be
connected to the
same
priority
level pin.
Polled
and
vectored operation should not
be
simultaneously enabled.
Operation with vectored
interrupts
is
preferred over polled
operation because the software overhead associated with identifying
the source
of
a polled
interrupt
can
slow
down
a system
significantly.
Unfortunately, vectored
interrupts
usually require additional
hardware
in
an
5100
machine.
Note
that
timer
interrupts
1
and
2
do
not
refer
to
AMD
9513
timers 1
and
2.
Rather,
interrupt
1
is
generated
(whE:n
enabled)
by
AHD
9513
timer 5.
Interrupt
2
is
generated,
when
enabled,
either
by
AMD
9513
timer 2
or
3 depending
on
how
jumpers
1T,
2T.
and
3T
are
set.
If
1T
and
2T
are
jumpered
together, timer 3
is
gated to the
interrupt
2
line
and
if
IT
and
3T
are
jumpered
together timer 2
is
gated to the
interrupt
2
line.