Specifications
15
Overlapped operation
is
not
recommended
when
the amplifier
settling
time
is
short. Taking the
MP6912A
as
an
example. the
mux
switching time
and
the amplifier
settling
time
combined
are 1 microsecond while the sample-
and-hold
circuit
requires 4 microseconds to complete a sampling. Since
the sample-and-hald cannot simultaneously
sample
one
voltage while holding
another. the 4 microsecond
sample
time
must
be
added
to the
MP6912A's
5 microsecond conversion time. Thus. overlapped operation saves only
1 microsecond
by
reducing the
total
Eyele time to 9 microseconds.
For
the
MP6912A
overlapped operation requires readjusting the
DlYOUT
time
from
its
normal
5 microseconds to 9 microseconds to give the sample-and-
hold
circuit
4 microseconds to
do
a sample. This marginal
improvement
in speed
can
cause
seriouts
problems
if
the
MUX
samples channels with widely
varying voltages. Since the sample-and-hold
is
not a
perfect
device
,
a
rapidly changing
signal
on
its
input
may
feed thru
slightly
and
cause
drastic
changes in the
resulting
value
of
the
AID
conversion
which
is
going
on
simultaneously.
Another
way
to increase throughput
is
to
have
the
CPU
wait for
the completion of conversions. This feature
is
enabled
by
closing
SW3-6
which
allows
IC4
pin 6 to lower the
CPU's
PROY
line.
This
causes the
CPU
to
enter
a wait
state
for
as
long as the
PRDY
line
is
low.
Also,
bit
7
of
the
command
register
must
be
a
one
giving
the
programmer
software control
of
this
feature. Bit 7 performs a
double function
on
the
A0212
since
it
also
is
used
to enable
an
interrupt
when
the
DONE
flop
is
set.
Because
of
this,
interrupts
caused
by
the
DONE
flop
must
be
disabled.
For
vectored
interrupts
this
is
easily
achieved
by
not connecting the
DONE
pin
on
the
vectored
interrupt
header.
If
polled
interrupts
from
some
of
the
remaining
interrupt
sources are desired
at
the
same
time
,
the wait
feature
;s
enabled, then the trace
from
IC4
pin 3
must
be
cut.
Programming
is
arranged such
that
all
necessary setup operations
are
performed
first,
followed
by
software generation
of
the
AID
strobe pulse
if
that is
the strobe source used.
Finally,
for
sixteen
bit
transfers,
a read
instruction
to port 4
is
executed.
This causes the signal
ADR
to propagate through
IC13
and
IC15
to
make
IC4
pin 4 true (high).
If
bit
7 of the
command
register
1C26
1s
high , then
IeS
pin
10
will
be
true
and
assuming
that
the
conversion
is
not
yet
complete
,
lC3
will cause
lCS
pin 9 to
be
true thus
making
the ready
line
low.
The
CPU
will
now
wait
until
the
DONE
flop is
set
making
the ready
line
high again.
The
CPU
will continue
where
it
left
off
by
immediately
finishing
the
instruction
to read the
new
number
in the data
register
thus
saving the time
that
would
otherwise
be
required to
test
the
DONE
bit
in the
status
register
for completion of a conversion.
The
situation
for
eight
bit
transfers
is
very
similar
except
that
the
wait occurs
when
the
CPU
reads the
lower
eight
data
bits
from
port
2.
When
the wait
is
over, the
CPU
then reads the high
eight
data
bits
from
port 4.
The
proposed
IEEE
SlOO
standard allows
ridiculously
little
setup time
on
the
PRDY
line
which
might
make
the
A02l2
harder to
use
with processors
which
follow
this
standard
too
closely.
;>C10sing
SW3-B
helps solve
this
problem
by
pulling the ready
line
~
down
sooner. Unfortunately. a
compromise
is
involved because the
ready
line
is
pulled
down
for
one
clock cycle during
PSYNC
at
the
beginning of every
instruction
whether
IC4
wants
the
CPU
to wait
or
not. This.
of
courseI
slows
down
the
CPU.
The
only
alternative
to
this
solution involves adding several additional
integrated
circuits
which
would
probably not
be
justified
for
most
users.