Specifications
9
bidirectional
trance;ver,
74lS245,
IC24
must
be
enabled
by
the
occurence
of
WR
and
BDSEl.
The
direction
of
IC24
will
be
from
the
5100
bus
to the timer as long as
PDBIN
is
false.
To
read
from
the
AM9513,
a
74L5244,
IC28,
enables the timer data onto the
5100
bus
when
the timer chip read
select
;s
true
and
5100
signal
SXTRQ
;s
false.
For
sixteen
bit
data
transfers,
le28 will never
be
enabled.
but
Je22
and IC24
will
be
active.
For
both
reads
and
writes,
lC24
behaves
exactly
as
it
did
for
eight
bit
transfers.
The
bidirectional
trance;ver, 74lS245,
Je22
;s
enabled
whenever
SXTRQ
(sixteen request)
is
true
and
the
AM9513
;s
selected
for
a read or a
write
operation.
The
timer chip read
line
;s
used
to control the
direction
of
Je22
so
that
it
receives
from
the
5100
bus
during a write
and
drives
the
bus
during a read.
All
sixteen
bit
transfers
to the
AD212
cause
an
acknowledgement
signal,
SIXTN.
to
be
placed
on
the
bus
by
IC4.
This signal
is
true
when
5XTRQ
and
B05EL
are true.
On
power-up. the
AM9513
assumes
8
bit
operation
and
must
be
enabled
for
16
bit
operation
by
setting
bit
13
of
the Master
Mode
register
as
detailed in the
AM9513
data sheet.
The
AM9513
is
potentially
the slowest
component
of
the
A02l2
and
may
not
be
fast
enough
to operate
at
full
speed with
fast
processors. Consequently. ICl.
IC9
and
IC1~
are
used
to
create
an
optional wait
state
by
lowering the ready
line.
Specifically.
flip-floD
lC10
is
clocked true during
P5YNC
by
the
falling
edge
of
the master timing signal
,
PHI,
and
false
again
on
the next
clock. Since
PSYNC
occurs for
one
clock period
at
the beginning
of
each
bus
cycle,
IC10
generates a signal called
"WAlT"
which
ca
n
be
Dsed
to
rna
ke
the proces sor
wa
it
for
one
clock cycle.
If
5W3-5
is
on, then
ICg
will lower the
ROY
line
when
the
AM9513
is
addressed. This will occur
when
WAIT,
A2.
A3
and
BDSEl
are
all
true.
In
most
cases
this
wait
state
will not
be
needed
and
SW3-5
can
be
left
open.
The
C5
(chip
select)
input
on
the
AM9513
is
always enabled, l
but
no
action occurs unless the read or write
lines
are active
also.
A
one
megahertz, crystal controlled clock
is
fed to the timer chip
by
using a 74lS74.
IC10,
to divide the
two
megahertz clock
from
the
5100
bus.
Each
of
the five counters in the
AM9513
has
three external
connections associated with
it.
One
is
an
output.
one
is
a count
source input.
and
one
is
a gated input.
All
of these are
externally available
after
being buffered
by
two
74L5244's,
IC17
and
IC18.
to a forty pin ribbon connector with interlaced grounds.
In
addition, a
programmable
divider signal called
FOUT
is
accessible
on
pin
20.
Five
volt
power
is
also available
on
this
connector
for
powering
a small
amount
of
external logic.
On
the order
of
100
milliamperes
may
be
drawn
from
this
source as long as
enough
air
is
provided to the regulator heatsink
on
the mother board to
keep
the regulator
cool
so
that
it
doesn't shut
down.
These
timer
chip connections
can
provide several
other
special functions
which
will
be
described in the
Interrupt
and
A/D
sections.