Specifications
Unfortunately,
the
above
technique
will
not
work
with
some
non-IEEE
compatible processors
such
as
Cromemco
1
s Single
Card
Comouter.
where
(incredibly)
the
status
signals
change
at
the
same
time
as
the timing signals
PDBIN
and
WR.
With
such
a processor,
it
is
not
possible to
reliably
use
the
false
state
of
a status
signal
as
our
above
selection
technique
does
because
circuit
delays
can
cause
skew
between
the timing anj
status
signals
thus
producing
momentary
false
selection
when
th~se
signals
change.
With
such
processors, the prooer
method
of
selection
is
to leave
SW5-5
open
(off)
and
use
SW1
to choose
memory
or
I/O. This
technique simply "ands" the
status
signals
SINP
and
SOUT
for
1/0-
mapped
or
SMEMR
and
SMEMW
for
memory-mapped
with the
results
of
the address
comparison
to
form
the signal
B8SEl,
which
selects
the
A02l2.
I/O
addressing is selected
when
the
right
two
switches
of
SWl
have
the
lower
part
of
their rockers depressed. Notice that
neither
of
the
above
selection
methods
~ver
have
SW5-5
on
while
SW1
is
connected to
SMEMW.
This
combination should rarely
work
properly
due
to the unique timing
of
SMEMW.
The
74LS244
acts
only
as
a receiver for these
and
other signals to minimize
the load
on
the
SlOO
bus.
When
the four
DM8136
YCs
all
find a true comparison, their
open-collector outputs
go
high
and
they allow the signal
BOSEL
to
become
true. This si9na1 enables
five
other chips,
most
important
of
which
are the
two
74LS13B
address decoders,
IC11
and
IC12.
These
circuits
decode
address
lines
A1,
A2
and
A3
to
produce
eight possible
read
functions
from
YC12
and
eight
possible write
functions
from
ICll. This
is
done
by
enabling
IC11
with the
WR
signal
and
IC12
with the
POBIN
signal.
The
address
line
AD
is
not
used
in the decoding process because the
AD212
is
compatible with
sixteen
bit
processors
where
AD
is
undefined during sixteen
bit
transfers. This causes the
AD212's
functions to
be
addressable a
.,11
pairs
of
address locations rather
than
at
a single location
as
~
indicated in the description
of
the
registers.
Activation
of
various functions
by
the 74lS138
1
s
is
straightforward in
most
cases
where
a
register
is
loaded
or
read
or
a
flip-flop
cleared.
The
AM9513
timer chip
has
two
read
and
two
write addresses.
Selection
of
these
is
accomplished
by
the
74LS08,
ICa,
which
is
connected in
an
nOR"
configuration
between
the 74lS138
and
the
AM9S13
and
thus
enables
the
timer chip for
either
of
two
addresses. Selection
of
one
of
these
two
addresses
is
determined
by
A1
which
controls the
C/O
(control/data)input
on
the
AM9513.
4.
AM9513
Timer
Circuit
The
AM9513
is
capable
of
performing
either
eight
or sixteen
bit
transfers to the
SlOO
bus. Considering
eight
bit
transfers
first.
one
finds that the chip
does
these using the bidirectional
data
lines
OBO
through
OB7.
The
most
significant
data
lines
must
be
held high during
this
time. This
is
done
by
using
RP5
to pull
them
up
while
IC22
is
disabled.
To
write to the timer
I.C.,
the
a