Specifications
3.
Address
Decoding
The
location
of
the various
AD212
registers in the 5-100
address space
is
determined
by
the
five
DIP
switches
5Wl-5W5
on
the
mother
board.
(See
AD212
Mother
Board
Switch Assignments.)
These
switches allow placement
of
the registers
anywhere
in
the
memory
or
I/O
space
of
a conventional or extended
memory
system.
Address
comparison
is
done
using four
DM8136
ICs
which
are designated
IC14. IC16,
IC21
and
IC31.
These
chips find a
comparison
on
a given
address
line
to
be
satisfied
(true)
when
a
high
input
from
the
S-lOO
bus
has
the
corresponding
DIP
switch position
OFF.
The
AD212
address
space
may
be
conceptually divided into three
groups
of
eight
lines
each.
The
least
significant
group.
AD
through
A7
,
are always
used
no
matter
how
the
A0212
is
configured.
The
middle
group,
AS
through
A1S
,
is
active
when
memory-mapped
addressing
is
selected
on
a
computer
system
of
conventional
size
or
when
I/O
mapped
addressing
is
selected
on
a
newer
system
having
sixteen
bits
of
I/O
addressing
caoability.
The
most
significant
lines,
Al6
through
A23.
are only
used
on
extended
memory
systems
where
meroory-mapped
addressing
is
chosen.
To
configure the
AD212
in
an
eight
bit
I/O
space,
all
address
comparators are disabled except for
IC31
by
opening
SW4-7
(position 7
of
switch 4)
and
SW2-7.
Sixteen
bit
memory
or
110
mapped
operation
is
specified
by
closing
SW4-7.
opening
SW2-7.
and
setting
the
left
two
switches
of
SWl
such
that the
lower
side
of
the rockers are
depressed. This simultaneously disconnects
A16
and
Al7
from
the
bus
while allowing
A14
and
A15
of
IC16
and
all
inputs to
IC21
to
contribute to the comparison.
To
operate the
AD2l2
in a
24
bit
extended
memory-mapped
system,
the
remainina
eight
most
significant
address
lines
must
be
enabled.
This
is
done
by
closing
SW4-7
and
SW2-7
and
by
setting
the
left
two
switches
of
SWl
such
that the
upper
side
of
the rockers are
depressed.
The
cboice
of
memory
or
I/O-mapped
operation
is
determined
by
the
settings
of
SW5-5
and
the
right
two
switches of
SW1.
The
IEEE
SlOO
standard
allows
5MEMW
to
rise
very
late
in
a write cycle
such
that
the
AD2l2
may
not
have
sufficient
set
up
time
for
certain functions
when
used
with
fast
processors
if it
is
required
to
wait for the leading
edge
of
SMEMW.
Consequently, the preferred
method
of
selection
is
to
have
SWl
permanently
set
to
SOUT
and
SINP
while
SW5-5
is
used
to
make
the choice
between
memory
or
110.
In
this ease,
memory-mapped
operation
is
selected
when
SWS-5
is
on.
This
scheme
eliminates a possible timing
problem
by
eliminating the
use
of
the
SMEMW
signal,
but
assumes
that
SINP
and
SOUT
are
stable
during
POBIN
and
WR,
respectively.
For
most
processors (of
if
you
didn't
get the full
gist
of
the
above)
set
SWl
for
SOUT
and
SINP
(switches are
down
towared
edge
connector)
and
set
SW5-5
ON
for
memory-mapDed
operation
and
SW5-5
OFF
for
I/O-mapped
operation.
7