Installation manual

2–30 Hardware installation
Note: The DAP does not pass auxiliary data bits separately under any condition. If these bits are being
used in your facility for intercom or other data the “Force 20 bit” mode should be used to prevent any data
or noise in the auxiliary bits from causing increased distortion or noise in the main audio channel.
Force 24 Bit
This setting forces all 24 bits of input sample data to be passed to the digital signal processing stages that follow.
This setting should be used when all data presented to the DAP has between 16 and 24 bits of significant information
and there are no auxiliary data or intercom channels used in the AES/EBU bit stream.
Note: If auxiliary data is present it will cause increased noise or distortion in the audio data as the DAP
cannot differentiate between auxiliary data and actual audio sample data.
V Bit Enable
The AES/EBU data stream contains a bit called the data “Valid” bit for each audio sample. This bit can be used to show
a damaged sample, or that the data is invalid for one reason or another. Normal operation for the DAP is to ignore this
bit and use any audio sample data that is present. However, the DAP can be configured to use the “V” bit to mute all audio
samples that arrive; this is done using the Digital Audio Setup table (page 3–41). When set for “Enable,” normal audio
will pass unless the “V” bit is set. If the V bit indicates invalid audio sample data, all bits in the data will be set to “0’s”
before being passed to the digital signal processing sections. The factory default is to ignore the “V” bit.
Rate Conversion
In order to provide the maximum flexibility in your installation, the DAP incorporates integral sample–rate convertors.
The rate convertors are primarily used to provide a solution for asynchronous input signals. If an input signal to the DAP
is synchronous, all data is passed directly to the digital signal processing stages. If an incoming signal is asynchronous
with the reference provided to the DAP, then an input detector senses the condition and switches the signal to sample
rate convertor. The rate convertor then provides a new signal to the digital signal processing stages that is “re–synchro-
nized” to the reference signal.
Sample rate conversion is not exact, even in the digital domain, and therefore introduces some distortion. This distortion
is very small, and in many cases is less than would be introduced by using a digital–to–analog and analog–to–digital
convertor to re–synchronize the signal. Because of this small distortion, it was felt that the rate–convertors should be
bypassed when not needed to preserve the original signal integrity. The rate convertors are also only good to 20 bit resolu-
tion and therefore would greatly reduce the accuracy and dynamic range of a 24 bit input signal.
Each input stage in the DAP has a lock detector that determines if the incoming signal is locked to the reference. If it
is locked, then the signal is passed untouched to the digital signal processors. If it is not locked, then the signal is routed
to the sample rate convertors. Since the rate convertor has a small amount of time delay to accomplish its task, the signal
that comes out is slightly delayed from the original. Therefore, the switch between the input and the output of the rate
convertor is not silent but may have a slight glitch if it occurs during a signal.
Normally the DAP is operated by switching a signal on the “preset” bus and placing it on the “program” bus by initiating
a transition. This is the desired mode of operation because the sample rate convertor requires a finite time before it pro-
duces a good output signal, and also a time required for the lock detectors to determine a locked condition. If sources
are selected on preset, there will usually be enough time for this settling to occur before the signal is placed on program
by making a transition.