Installation manual

Hardware installation2–27
2. 48 kHz NTSC Video. This mode utilizes a local video PLL locking to Horizontal sync which is then compared to
a divided down version of the internal 12.288 MHz clock. The 12.288 MHz clock is generated by a low–jitter sec-
ondary PLL which provides approximately equivalent performance to the AES low–jitter PLL. This is a frequency
lock only and does not attempt to define a specific relationship between video frames and audio frames (there is
currently no industry standard defining this relationship). As such this mode should only be used when the DAP
is acting as a master sync generator. If multiple DAP processors are used in an installation, only one should lock
to video reference and the rest should be locked to the master DAP 3500 using the AES/EBU reference output.
When unlocked, the internal frequency defaults to 48 kHz.
3. 48 kHz PAL Video. This mode utilizes a local video PLL locking to Horizontal sync which is then compared to
a divided down version of the internal 12.288 MHz clock. The 12.288 MHz clock is generated by a low–jitter sec-
ondary PLL which provides approximately equivalent performance to the AES low–jitter PLL. This is a frequency
lock only and does not attempt to define a specific relationship between video frames and audio frames (there is
currently no industry standard defining this relationship). As such this mode should only be used when the DAP
is acting as a master sync generator. If multiple DAP processors are used in an installation, only one should lock
to video reference and the rest should be locked to the master DAP using the AES/EBU reference output. When
unlocked, the internal frequency defaults to 48 kHz. See notes in Step 11 below.
4. 48 kHz Internal. This allows the internal low–jitter PLL to run without external reference. A trimmer is set at the
factory for correct center frequency. Normally this mode is used only for factory testing. (This mode forces all in-
puts to be asynchronous to the internal reference.)
5. 48 kHz AES AUTO. This is the factory default setting and the preferred mode. This mode provides the same ultra
stable low–jitter reference at a sample rate of 48 kHz as selection #1, but has a much larger lock range of approxi-
mately + or – 4%. When the reference is within approx. + or – 200 ppm of 48 kHz, then the DAP automatically
selects the super low–jitter secondary PLL. Otherwise, when outside the limits of + or – 200 ppm, the DAP remains
locked up to a range of + or – 4 % using only the primary PLL. When using the primary PLL the resulting internal
clocks are not as low in jitter performance as when the secondary PLL is used, but the DAP will continue to operate
correctly. When unlocked, the internal frequency defaults to 48 kHz.
6. 44.1 kHz Narrow. This mode provides an ultra stable low–jitter reference at a sample rate of 48 kHz. The lock range
of the internal PLL is approximately + or – 200 ppm. This mode is normally used only for testing in the factory.
When unlocked, the internal frequency defaults to 44.1 kHz.
7. 44.1 kHz Internal. This allows the internal low–jitter PLL to run without external reference. A trimmer is set at the
factory for correct center frequency. Normally this mode is used only for factory testing. When unlocked, the inter-
nal frequency defaults to 44.1 kHz. (This mode forces all inputs to be asynchronous to the internal reference.)
8. 44.1 kHz AES AUTO. This mode provides the same ultra stable low–jitter reference at a sample rate of 44.1 kHz
as selection #1, but has a much larger lock range of approximately + or – 4%. When the reference is within approx.
+ or – 200 ppm of 44.1 kHz, then the DAP automatically selects the super low–jitter secondary PLL. Otherwise,
when outside the limits of + or – 200 ppm, the DAP remains locked up to a range of + or – 4 % using only the primary
PLL. The internal clocks are not as low jitter as when using the secondary PLL, but the DAP will continue to operate
correctly. When unlocked, the internal frequency defaults to 44.1 kHz.
9. AES Automatic. This mode provides operation at all sample rate frequencies between 30 and 50 kHz. If the refer-
ence is within approximately + or – 200 ppm of either 48 or 44.1 kHz, the DAP will automatically turn on the sec-
ondary low–jitter PLL circuits and lock. This provides the best operation for those conditions that may have widely
varying AES/EBU references. The only problem is that when unlocked, the internal frequency defaults to some-
thing less than 30 kHz.