Data Sheet

HEF4049B_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 11 November 2008 6 of 11
NXP Semiconductors
HEF4049B
Hex inverting buffers
Test data is given in Table 10.
Definitions for test circuit:
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
Fig 6. Load circuitry for switching times
V
DD
V
I
V
O
001aag182
DUT
C
L
R
T
G
Table 10. Test data
Supply voltage Input Load
V
I
V
M
t
r
, t
f
C
L
5 V to 15 V V
DD
0.5V
I
≤ 20 ns 50 pF