Data Sheet

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1. General description

The HEF4049B provides six inverting buffers with high current output capability suitable

for driving TTL or high capacitive loads. Since input voltages in excess of the buffers’

supply voltage are permitted, the buffers may also be used to convert logic levels of up to

15 V to standard TTL levels. Their guaranteed fan-out into common bipolar logic elements

is shown in Table 3.

It operates over a recommended V

power supply range of 3 V to 15 V referenced to V

(usually ground). Unused inputs must be connected to V

, V

, or another input. It is

also suitable for use over the industrial (−40 °C to +85 °C) temperature range.

2. Features

n Accepts input voltages in excess of the supply voltage

n Fully static operation

n 5 V, 10 V, and 15 V parametric ratings

n Standardized symmetrical output characteristics

n Operates across the full industrial temperature range −40 °C to +85 °C

n Complies with JEDEC standard JESD 13-B

n ESD protection:

u HBM JESD22-A114E exceeds 2000 V

u MM JESD22-A115-A exceeds 200 V

3. Applications

n LOCMOS (Local Oxidation CMOS) to DTL/TTL converter

n HIGH sink current for driving two TTL loads

n HIGH-to-LOW level logic conversion

4. Ordering information

HEF4049B

Hex inverting buffers

Rev. 05 — 11 November 2008 Product data sheet

Table 1. Ordering information

All types operate from

−

C to +85

Type number Package

Name Description Version

HEF4049BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4

HEF4049BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Summary of content (11 pages)

PAGE 1
HEF4049B Hex inverting buffers Rev. 05 — 11 November 2008 Product data sheet 1. General description The HEF4049B provides six inverting buffers with high current output capability suitable for driving TTL or high capacitive loads. Since input voltages in excess of the buffers’ supply voltage are permitted, the buffers may also be used to convert logic levels of up to 15 V to standard TTL levels. Their guaranteed fan-out into common bipolar logic elements is shown in Table 3.
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HEF4049B NXP Semiconductors Hex inverting buffers 5. Functional diagram 1A 2A 3A 4A 5A 6A 3 2 5 4 7 6 9 10 11 12 14 15 1Y 2Y 3Y 4Y 5Y input 6Y Y A 001aai331 Fig 1. Logic symbol VSS mna341 Fig 2. Logic diagram for one gate 001aae604 Fig 3. Input protection circuit 6. Pinning information 6.1 Pinning HEF4049B VDD 1 16 n.c. 1Y 2 15 6Y 1A 3 14 6A 2Y 4 13 n.c. 2A 5 12 5Y 3Y 6 11 5A 3A 7 10 4Y VSS 8 9 4A 001aae602 Fig 4. Pin configuration 6.
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HEF4049B NXP Semiconductors Hex inverting buffers Table 2. Pin description …continued Symbol Pin Description 1A to 6A 3, 5, 7, 9, 11, 14 input VSS 8 ground supply voltage n.c. 13, 16 not connected 7. Functional description Table 3. Guaranteed fan-out Driven element Guaranteed fan-out Standard TTL 2 74 LS 9 74 L 16 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min −0.
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HEF4049B NXP Semiconductors Hex inverting buffers 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH VIL VOH VOL IOH IOL Conditions |IO| < 1 µA HIGH-level input voltage |IO| < 1 µA LOW-level input voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current |IO| < 1 µA |IO| < 1 µA Tamb = 25 °C Tamb = 85 °C Min Max Min Max Min Max Unit 5V 3.5 - 3.
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HEF4049B NXP Semiconductors Hex inverting buffers Table 7. Dynamic characteristics …continued VSS = 0 V; CL = 50 pF; tr = tf ≤ 20 ns; Tamb = 25 °C; unless otherwise specified. Symbol tTHL Parameter Conditions HIGH to LOW output transition time see Figure 5 LOW to HIGH output transition time see Figure 5 VDD Extrapolation formula [1] 5V 10 V [1] Typ Max Unit 3 ns + (0.35 ns/pF)CL - 20 40 ns 3 ns + (0.14 ns/pF)CL - 10 20 ns 2 ns + (0.09 ns/pF)CL - 7 14 ns 10 ns + (1.
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HEF4049B NXP Semiconductors Hex inverting buffers VDD VI VO G DUT RT CL 001aag182 Test data is given in Table 10. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 6. Load circuitry for switching times Table 10. Test data Supply voltage 5 V to 15 V Input Load VI VM tr, tf CL VDD 0.5VI ≤ 20 ns 50 pF HEF4049B_5 Product data sheet © NXP B.V. 2008.
PAGE 7
HEF4049B NXP Semiconductors Hex inverting buffers 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.
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HEF4049B NXP Semiconductors Hex inverting buffers SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.
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HEF4049B NXP Semiconductors Hex inverting buffers 14. Abbreviations Table 11. Abbreviations Acronym Description DUT Device Under Test DTL Diode Transistor Logic ESD ElectroStatic Discharge HBM Human Body Model LOCMOS Local Oxidation CMOS MM Machine Model TTL Transistor Transistor Logic 15. Revision history Table 12.
PAGE 10
HEF4049B NXP Semiconductors Hex inverting buffers 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PAGE 11
HEF4049B NXP Semiconductors Hex inverting buffers 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . .