User manual

Connect Tech FreeForm/PCI-104 User Manual
Revision 0.07 19
FPGA Configuration
The Virtex-5 FPGA can be configured via two methods:
o JTAG programming chain, using P2
o SPI Flash, read on, power-up by FPGA
The configuration flash can be programmed (loaded) through three methods:
o JTAG programming chain (through FPGA), using P2
o Direct with cable, using P3 [No longer supported after in ISE 12.x and later]
o Indirect programming through FPGA, only possible after configuration is complete (refer
to reference design for more details)
To configure the FPGA via the JTAG / boundary scan programming chain, three items are required:
o FPGA bitstream (*.bit), generated at end FPGA implementation using ISE
o PLX 9056 boundary scan definition file (*.bdsl)
o Ethernet PHY boundary scan definition file
To program the SPI flash, a hex file must be generated (*.mcs) then written to the flash. To generate
the hex file, the following is required:
o FPGA Bitstream
o Setting PROM file format to MCS (important since bits are swapped)
o Setting SPI PROM density to 16M
o Setting SPI Flash type to M25P16
For a complete procedure, refer to Appendix A.
FPGA Ethernet MAC Addresses
The FreeForm/PCI-104’s FPGA contains 2 dual Tri-Mode Ethernet MACs. One dual MAC is
connected to the on-board Ethernet PHY, and the other is free for general use. In either case, the
Ethernet MAC address is set by the user application, either HDL or embedded software – it is not
hard coded as part of the FPGA silicon.
As such, the user is required to provide a valid Ethernet MAC address. If the end product usage is
in the public domain, then this Ethernet MAC address must have a registered IEEE OUI
designator.
If your organization or parent company does not have a registered IEEE OUI listing, please
contact Connect Tech Inc. to obtain a valid Ethernet MAC address for your product.