FreeForm/PCI-104 User Manual Connect Tech, Inc. 42 Arrow Road Guelph, Ontario Canada, N1K 1S6 Tel: 519-836-1291 800-426-8979 Fax: 519-836-4878 Email: sales@connecttech.com support@connecttech.com URL: http://www.connecttech.com CTIM-00040 Revision 0.
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Connect Tech FreeForm/PCI-104 User Manual Table of Contents Limited Lifetime Warranty ......................................................................................................... 2 Copyright Notice ........................................................................................................................ 2 Trademark Acknowledgment ..................................................................................................... 2 Customer Support Overview ......................
Connect Tech FreeForm/PCI-104 User Manual List of Tables Table 1: FreeForm/PCI-104 Components .................................................................................. 8 Table 2: Slot Selection (RSW1) ................................................................................................10 Table 3: FPGA Configuration Settings (J1) ..............................................................................10 Table 4: JTAG Programming Header Pinout (P2) ..................................
Connect Tech FreeForm/PCI-104 User Manual Introduction Connect Tech’s FreeForm/PCI-104 features Xilinx’s Virtex-5 multi-platform FPGA offering users a flexible, reconfigurable computing platform that also takes advantage of the high bandwidth capabilities of the PCI bus while communicating with various I/O interfaces. Product Features o o o o o o o o o o o o o o o PCI-104 form factor – 32-Bit/33MHz, both 3.
Connect Tech FreeForm/PCI-104 User Manual System Overview The following conceptual block diagram provides a high level overview of the FreeForm/PCI-104 and illustrates the general interconnection between components and connectors. For the actual orientation and description of components refer to Figure 2 and Table 1 respectively. PCI-104 Bus EEPROM (Config Registers) PCI Bus Interface [PLX 9056]s SPI Flash (FPGA Config.) 1x6 Header 100 Mhz Osc.
Connect Tech FreeForm/PCI-104 User Manual Figure 2: FreeForm/PCI-104 Layout Table 1: FreeForm/PCI-104 Components Connectors P1 P2 P3 P4 P5, P6 P7 P8 P9 P10 Jumpers /Switches RSW1 J1 Components D1-D4 D5 U4 U5 U10 U11 U12, U13 U14 U15, U16 U17 O1,O2, O3 Revision 0.
Connect Tech FreeForm/PCI-104 User Manual Reference Design The FreeForm/PCI-104 ships with a pre-installed reference design that is loaded into the FPGA’s configuration flash. This reference design demonstrates how to interface the FreeForm/PCI-104 (Virtex-5 FPGA) with the PLX PCI 9056 PCI to Local Bus Bridge, as well as the various peripherals. The PLX 9056 provides a generic local bus that is capable of operating at up to 66MHz (this design forwards a 50MHz clock to the PLX).
Connect Tech FreeForm/PCI-104 User Manual Hardware Description The following sections describe the function of all switches/jumpers and provide details on connector pinouts. Jumpers and Switches Slot Selection (RSW1) This rotary switch selects a slot position in the PCI-104 stack. When mounting on a PCI adapter card, ensure slot one is selected. Table 2: Slot Selection (RSW1) Position Slot 0,4 0 1,5 1 2,6 2 3,7 3 FPGA Configuration Settings (J1) Jumper J1 is used to control FPGA configuration.
Connect Tech FreeForm/PCI-104 User Manual Connector Pinouts PCI-104 Header (P1) Refer to PCI-104 specifications. Note: The FreeForm/PCI-104 only requires the 5V power supply,. The board is compatible with PCI-104 mother boards that supply just 5V or both 3.3V & 5V. JTAG Programming Header (P2) Use P2 to configure the FPGA via JTAG. Refer to FPGA Configuration for more information. Power pins are for voltage reference only; they do not provide power to the configuration circuitry.
Connect Tech FreeForm/PCI-104 User Manual High-speed Serial (P4) The high-speed serial connector carries four Rocket (GTP) I/O channels, each with a dedicated transmit and receive differential pair. These channels are capable of operating up 3.125 Gbps, depending on configuration. For more information on Rocket I/O capabilities, visit the Xilinx website: http://www.xilinx.
Connect Tech FreeForm/PCI-104 User Manual Top View RS-485 Headers (P5, P6) Table 7: RS-485 Port 1 Pinout (P5) Pin 1 2 3 4 5 6 7 8 9 10 Signal RXD+1 Direction Input RXD-1 Input TXD+1 Output TXD-1 Output GND Power 1 10 P5 485 Port 0 Top View Table 8: RS-485 Port 2 Pinout (P6) Pin 1 2 3 4 5 6 7 8 9 10 Revision 0.
Connect Tech FreeForm/PCI-104 User Manual GPIO Header (P7) When in differential mode, the GPIO header positive (P) and negative (N) signals are adjacent on a standard ribbon cable. Note that the GPIO voltage level is set via hardware. o o Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Revision 0.07 FCG001: L12 populated, enabling 2.5V I/O, including LVDS FCG002: L13 populated, enabling 3.
Connect Tech FreeForm/PCI-104 User Manual Side View External Power Connector (P8) The external connector provides 5V to the power regulation circuitry. The external power connector should only be used when the FreeForm/PCI-104 is being programmed outside of a PCI/PCI-104 system. Pin Table 10: External Power Connector Pinout (P8) Signal Direction 1 2 3 5V Power GND Power 4 VIO (connect to 5V) Power 1 2 3 4 P8 Standalone Power Input It is recommended that a Connect Tech Inc.
Connect Tech FreeForm/PCI-104 User Manual Connector’s Mating Components and Cables The following table lists the manufacturer and part number for connectors on the FreeForm/PCI-104, as well as potential mating components. Table 11: Connector Mate Listing Connector P2 P3 P4 P5/P6 P7 Component on FreeForm/PCI-104 Samtec TSW-107-07-L-S (0.100” pitch, 1x7) Samtec TSW-106-07-L-S (0.100” pitch, 1x6) Samtec QSE-014-01-L-D-DP-A (0.8mm pitch, 2x14, arranged as 14 differentials pairs) Samtec TSW-105-07-L-D (0.
Connect Tech FreeForm/PCI-104 User Manual Hardware Installation Before installing the FreeForm/PCI-104 into a PCI-104 stack, ensure the following: o o Slot selection is properly set using the rotary switch RSW1. FPGA configuration jumper J1 is set to read from flash. Once installed in the system and power is applied, the LED D1 will illuminate to indicate that FreeForm/PCI-104 is functioning.
Connect Tech FreeForm/PCI-104 User Manual Software Installation FPGA Development Environment FreeForm/PCI-104 has been developed with Xilinx WebPACK 9.2, available free of charge at: http://www.xilinx.com/ise/logic_design_prod/webpack.htm PLX Software Development Kit (SDK) PLX provides a software development kit (SDK) to aid in the creation of applications using the PLX 9056 bridge. The SDK provides a generic driver for Windows 2000/XP and Linux.
Connect Tech FreeForm/PCI-104 User Manual FPGA Configuration The Virtex-5 FPGA can be configured via two methods: o o JTAG programming chain, using P2 SPI Flash, read on, power-up by FPGA The configuration flash can be programmed (loaded) through three methods: o o o JTAG programming chain (through FPGA), using P2 Direct with cable, using P3 [No longer supported after in ISE 12.
Connect Tech FreeForm/PCI-104 User Manual Power and Thermal Considerations The FreeForm/PCI-104’s Virtex-5 FPGA is a versatile, flexible device, with many built-in features like termination, PLLs, and high speed gigabit transceivers. The drawback of these on-chip features is that they consume a lot of power and hence dissipate a lot of heat. As a result Connect Tech, is recommending the installation of a heatsink, included with the product (see section Heat Sink Installation).
Connect Tech FreeForm/PCI-104 User Manual Specifications Programmable FPGA Virtex-5 FPGA LX30T Virtex-5 FPGA LX50T Virtex-5 FPGA FX30T PCI-104 Bus 32 bit / 33 MHz 3.
Connect Tech FreeForm/PCI-104 User Manual Appendix A: ISE iMPACT Procedures IMPORTANT: As of the writing of this document, there are issues with Xilinx iMPACT in ISE 14.x when using in-direct programming of M25P## SPI flashes. It is recommended that you download ISE 13.4 lab tools to program the SPI flash. ISE 14.x can still be used for development and bitstream generation. Preparing the iMPACT Project 1) Connect the JTAG programming cable to P2 ensuring that all JTAG signals align correctly.
Connect Tech FreeForm/PCI-104 User Manual 5) When prompted with the following messages, click OK and Cancel 6) Right click on the FPGA, and click ‘Assign new Configuration File’ 7) Browse to the reference design directory, and select the bitstream (.bit) Example: {REFDIR}\fpga\\ise_projects\ref_design_fcg001rd\ref_design.bit 8) A prompt will ask if you wish to attach a SPI file or BPI Prom. Click Yes. 9) Browse to the reference design directory, and select the prom bile (.
Connect Tech FreeForm/PCI-104 User Manual 11) Right click on the second device in the JTAG chain and click ‘Assign New Configuration File’ 12) Browse to the bsdl folder and select PCI9056BA.bsd Example: {REFDIR}\fpga\bsdl\PCI9056BA.bsd 13) Right click on the second device in the JTAG chain and click ‘Assign New Configuration File’ 14) Browse to the bsdl folder and select DP83849IVS.bsd. Example: {REFDIR}\fpga\bsdl\ DP83849IVS.
Connect Tech FreeForm/PCI-104 User Manual Programming the FPGA 1) Connect the JTAG programming cable to P2 ensuring that all JTAG signals align correctly. Note that P2 also has the TRST signal on pin 1, which is not part of Xilinx’s Parallel or USB programming cables. 2) Remove all jumpers from J1; to ensure the flask is not loaded into the FPGA. 3) Open the recently saved iMPACT project file Example: {REFDIR}\fpga\\ise_projects\ref_design_fcg001rd\ ref_design_fcg001rd.
Connect Tech FreeForm/PCI-104 User Manual 7) Once the FPGA has been programmed successfully, you will see ‘Program Succeeded’ INFO:iMPACT - Current time: 2013-03-25 4:49:45 PM // *** BATCH CMD : Program -p 1 -v -dataWidth 1 PROGRESS_START - Starting Operation. Maximum TCK operating frequency for this device chain: 10000000. Validating chain... Boundary-scan chain validated successfully. 1: Device Temperature: Current Reading: -273.00 C 1: VCCINT Supply: Current Reading: 0.
Connect Tech FreeForm/PCI-104 User Manual Programming the Flash 1) Connect the JTAG programming cable to P2 ensuring that all JTAG signals align correctly. Note that P2 also has the TRST signal on pin 1, which is not part of Xilinx’s Parallel or USB programming cables. 2) Add the appropriate jumper to J1. 3) Open the recently saved iMPACT project file Example: {REFDIR}\fpga\\ise_projects\ref_design_fcg001rd\ ref_design_fcg001rd.
Connect Tech FreeForm/PCI-104 User Manual 6) Right click on the flash and perform a blank check. 7) If the part is blank you will see: INFO:iMPACT - Current time: 2013-03-25 3:24:31 PM // *** BATCH CMD : BlankCheck -p 1 -spionly PROGRESS_START - Starting Operation. Maximum TCK operating frequency for this device chain: 10000000. Validating chain... Boundary-scan chain validated successfully. 1: Device Temperature: Current Reading: -273.00 C 1: VCCINT Supply: Current Reading: 0.
Connect Tech FreeForm/PCI-104 User Manual 9) If the programming is succesful you will see: INFO:iMPACT - Current time: 2013-03-25 4:51:55 PM // *** BATCH CMD : Program -p 1 -v -dataWidth 1 -spionly -e -v -loadfpga PROGRESS_START - Starting Operation. Maximum TCK operating frequency for this device chain: 10000000. Validating chain... Boundary-scan chain validated successfully. 1: Device Temperature: Current Reading: -273.00 C 1: VCCINT Supply: Current Reading: 0.000 V 1: VCCAUX Supply: Current Reading: 0.
Connect Tech FreeForm/PCI-104 User Manual Generating a PROM (MCS) File 1) Double click PROM File Formatter in the Flows window. 2) Select ‘Configure Single FPGA’, then click the green arrow 3) Select a storage device size of 32M (or 16M) then click the green arrow Note: To identify the flash size, refer to Appendix D: Identifying Configuration Flash Size Revision 0.
Connect Tech FreeForm/PCI-104 User Manual 4) Provide a name and location for the output mcs file, the click OK. 5) Click OK when prompted to add a new device 6) Browse to the reference design directory, and select the bitstream (.bit) Example: {REFDIR}\fpga\\ise_projects\ref_design_fcg001rd\ref_design.bit 7) When asked to add another device, click no, then click ok to complete the setup. 8) Under iMPACT processes, ‘click generate file’.
Connect Tech FreeForm/PCI-104 User Manual Appendix B: Power calculations Scenario 1: Heatsink attached, 250 LFM Revision 0.
Connect Tech FreeForm/PCI-104 User Manual Scenario 2: No Heatsink, 250 LFM Revision 0.
Connect Tech FreeForm/PCI-104 User Manual Scenario 3: No heatsink, 0 LFM Revision 0.
Connect Tech FreeForm/PCI-104 User Manual Appendix C: Hardware Changes from Revision B This appendix lists the changes between hardware revision B and hardware revision C, D, E. The following is a summary of changes: PCB requires only 5V over PCI-104; it previously required 3.3V and 5V A dedicated local bus oscillator was added to generate 50Mhz. A clock is no longer forwarded from FPGA to the PLX PCI 9056.
Connect Tech FreeForm/PCI-104 User Manual Reference Design The top level reference design contains a generic parameter which will correctly configure the FPGA for Revision B or Revision C. A separate constraint file UCF is created for Revision B and Revision C, which need to be added to the ISE project manually. Revision B Local Clock Generation Pin Signal Name Y21 lb_lclkfb A20 lb_lclko_loop B21 lb_lclko_plx Revision C Local clock generated in FPGA and forwarded to PLX bridge.
Connect Tech FreeForm/PCI-104 User Manual Hardware Description Connector Pinouts High-speed Serial (P4) The sideband LVCMOS signals (HSS) have been rearranged so that when two FreeForm units are connected: HSS_USER_IO(0) maps to HSS_USER_IO(2) HSS_USER_IO(1) maps to HSS_USER_IO(3) Also, 3.3V pins replace the GND pins; this is because the connector has embedded GND blades.
Connect Tech FreeForm/PCI-104 User Manual External Power Connector (P8) The connector no longer enables 3.3V regulation – it is always enabled. Revision B Pin Signal Revision C, D Pin Signal 1 5V 1 2 3.3 enable (connect to 5V) 2 5V 3 GND 3 GND 4 VIO (connect to 5V) 4 VIO (connect to 5V) Specifications Revision B Power Requirements +3.
Connect Tech FreeForm/PCI-104 User Manual Appendix D: Identifying Configuration Flash Size The FreeForm/PCI104 is built with either M25P32 M25P16 32 Mbit 16 Mbit Rev D (> 09/2009), Rev E Rev B, Rev C, Rev D (< 09/2009) Both flash sizes are more than large enough to store a bitstream for any FreeForm/PCI104 variant. However, the correct flash size will need to be identified for programing. To identify the flash, find U10 on the backside of the board and read the top side marking.
