User's Manual

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Flow Control
AT+i Programmer‘s Manual Version 8.32 24-6
24.5 Host iChip Hardware Flow Control
As an alternative to the software flow control method, which requires some software
attention on behalf of the host, iChip offers a hardware flow control mode.
This mode is selected by setting iChip‘s FLW parameter Bit 0, using the
AT+iFLW
command. Note that to set FLW Bit 0, the ~CTSH signal needs to be LOW (enabled),
otherwise iChip returns I/ERROR (063). This convention safeguards iChip from lockup,
which may arise if FLW Bit 0 is set while the ~CTSH signal is constantly HIGH.
For hardware flow control to operate properly, the ~CTS and ~RTS signals between the
host and iChip UARTS must be interconnected.
The iChip ~CTSH and ~RTSH signals can be shorted to circumvent hardware flow
control.
Under this mode, iChip assumes that the host transmission might be paused by de-
asserting the ~CTS signal. The host must adhere to this convention. Most UARTs support
hardware flow control. However, if this is not the case, iChip‘s ~CTS signal must be
monitored by the host software on a general purpose I/O.
The host can also pause iChip by de-asserting its ~CTS signal.
If a transmission error occurs during processing of a send command (
EMB, SSND,
TBSN, FSND), iChip accepts all remaining characters pertaining to the current command
(as specified by the <sz> parameter) before returning the relevant I/ERROR response.
Figure 24-3 Minimum Hardware Flow Control Connections
HOST
iChip
~CTS
~RTS
~Tx
~Rx
~CTSH
~RTSH
~Tx
~Rx