User`s guide

Copyright © 2012 congatec AG TCEDm10 82/94
9.4.9.2 PCI Express Port Submenu
Feature Options Description
PCI Express Port x Disabled
Enabled
Enable or disable the respective PCI Express port x.
Port x IoxAPIC Disabled
Enabled
Enable or disable PCI Express Root Port x I/O APIC.
Automatic ASPM Manual
Auto
Automatically enable ASPM based on reported capabilities and known issues.
ASPM L0s Disabled
Root Port Only
Endpoint Port Only
Both Root And
Endpoint Ports
Enable PCIe ASPM L0s
ASPM L1 Disabled
Enabled
Enable PCIe ASPM L1.
URR Disabled
Enabled
PCI Express Unsupported Request Reporting Enable/Disable.
FER Disabled
Enabled
PCI Express Device Fatal Error Reporting Enable/Disable.
NFER Disabled
Enabled
PCI Express Device Non-Fatal Error Reporting Enable/Disable.
CER Disabled
Enabled
PCI Express Device Correctable Error Reporting Enable/Disable.
CTO Disabled
Enabled
PCI Express Completion Timer TO Enable/Disable.
SEFE Disabled
Enabled
Root PCI Express System Error on Fatal Error Enable/Disable.
SENFE Disabled
Enabled
Root PCI Express System Error on Non-Fatal Error Enable/Disable.
SECE Disabled
Enabled
Root PCI Express System Error on Correctable Error Enable/Disable.
PME SCI Disabled
Enabled
PCI Express PME SCI Enable/Disable.
Hot Plug Disabled
Enabled
PCI Express Hot Plug Enable/Disable.
Extra Bus Reserved 0-7 Extra Bus Reserved (0-7) for bridges behind this Root Bridge. Default value is 0
Reserved Memory [1-20] Reserved Memory and Prefetchable Memory (1-20MB) Range for this Root Bridge. Default Value is 1MB.
Reserved I/O 4K,8K,2K,16K,20K Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.