User`s guide

Copyright © 2012 congatec AG TCEDm10 59/94
Table 24 DisplayPort (DP) Signal Descriptions
Signal Pin # Description I/O PU/PD Comment
DP1_LANE3+
DP1_LANE3-
D36
D37
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI1_PAIR3+ and DDI1_PAIR3-.
O PCIE
DP1_LANE2+
DP1_LANE2-
D32
D33
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI1_PAIR2+ and DDI1_PAIR2-.
O PCIE
DP1_LANE1+
DP1_LANE1-
D29
D30
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI1_PAIR1+ and DDI1_PAIR1-.
O PCIE
DP1_LANE0+
DP1_LANE0-
D26
D27
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI1_PAIR0+ and DDI1_PAIR0-.
O PCIE
DP1_HPD C24 Detection of Hot Plug / Unplug and notication of the link layer.
Multiplexed with DDI1_HPD.
I 3.3V PD 1M
DP1_AUX+ D15 Half-duplex bi-directional AUX channel for services such as link
conguration or maintenance and EDID access.
I/O PCIE PD 100k
DP1_AUX- D16 Half-duplex bi-directional AUX channel for services such as link
conguration or maintenance and EDID access.
I/O PCIE PU 100k
3.3V
DP1_AUX- is a boot strap signal (see note below).
DP enable strap is already populated.
DP2_LANE3+
DP2_LANE3-
D49
D50
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI2_PAIR3+ and DDI2_PAIR3-
O PCIE
DP2_LANE2+
DP2_LANE2-
D46
D47
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI2_PAIR2+ and DDI2_PAIR2-
O PCIE
DP2_LANE1+
DP2_LANE1-
D42
D43
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI2_PAIR1+ and DDI2_PAIR1-
O PCIE
DP2_LANE0+
DP2_LANE0-
D39
D40
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI2_PAIR0+ and DDI1_PAIR0-
O PCIE
DP2_HPD D44 Detection of Hot Plug / Unplug and notication of the link layer.
Multiplexed with DDI2_HPD.
I 3.3V PD 1M
DP2_AUX+ C32 Half-duplex bi-directional AUX channel for services such as link
conguration or maintenance and EDID access.
I/O PCIE PD 100k
DP2_AUX- C33 Half-duplex bi-directional AUX channel for services such as link
conguration or maintenance and EDID access.
I/O PCIE PU 100k
3.3V
DP2_AUX- is a boot strap signal (see note below).
DP enable strap already populated.
DP3_LANE3+
DP3_LANE3-
C49
C50
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI3_PAIR3+ and DDI3_PAIR3-.
O PCIE Not supported
DP3_LANE2+
DP3_LANE2-
C46
C47
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI3_PAIR2+ and DDI3_PAIR2-.
O PCIE Not supported