User`s guide

7.1 A-B Connector Signal Descriptions

Table 3 Intel

High Denition Audio Link Signals Descriptions

Signal Pin # Description I/O PU/PD Comment

AC/HDA_RST# A30 Intel

High Denition Audio Reset: This signal is the master hardware reset

to external codec(s).

O 3.3VSB AC’97 codecs are not supported.

AC/HDA_SYNC A29 Intel

High Denition Audio Sync: This signal is a 48 kHz xed rate sample

sync to the codec(s). It is also used to encode the stream number.

O 3.3V AC’97 codecs are not supported.

AC/HDA_SYNC is a boot strap signal

(see note below)

AC/HDA_BITCLK A32 Intel

High Denition Audio Bit Clock Output: This signal is a 24.000MHz

serial data clock generated by the Intel

High Denition Audio controller.

O 3.3V AC’97 codecs are not supported.

AC/HDA_SDOUT A33 Intel

High Denition Audio Serial Data Out: This signal is the serial TDM

data output to the codec(s). This serial output is double-pumped for a bit rate

of 48 Mb/s for Intel

High Denition Audio.

O 3.3V AC’97 codecs are not supported.

AC/HDA_SDOUT is a boot strap signal

(see note below)

AC/HDA_SDIN[1:0] B29-B30 Intel

High Denition Audio Serial Data In [1:0]: These signals are serial

TDM data inputs from the two codecs. The serial input is single-pumped for a

bit rate of 24 Mb/s for Intel

High Denition Audio.

I 3.3V AC’97 codecs are not supported.

AC/HDA_SDIN2 is not supported

Note

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module.

For more information refer to section 7.5 of this user’s guide.