User`s guide

Boot Strap Signals7.5

Table 26 Boot Strap Signal Descriptions

Signal Pin # Description of Boot Strap Signal I/O PU/PD Comment

AC_SYNC A29 AC ’97/Intel

High Denition Audio Sync: This signal is a 48 kHz xed rate sample

sync to the codec(s). It is also used to encode the stream number.

O 3.3V AC_SYNC is a boot strap signal (see

caution statement below)

AC_SDOUT A33 AC ’97/Intel

High Denition Audio Serial Data Out: This signal is the serial TDM

data output to the codec(s). This serial output is double-pumped for a bit rate of 48 Mb/s

for Intel

High Denition Audio.

O 3.3V AC_SDOUT is a boot strap signal (see

caution statement below)

ATA_ACT# A28 ATA (parallel and serial) or SAS activity indicator, active low. OC 3.3V ATA_ACT# is a boot strap signal (see

caution statement below)

SPKR B32 Output for audio enunciator, the “speaker” in PC-AT systems O 3.3V SPEAKER is a boot strap signal (see

caution statement below)

PEG_LANE_RV# D54 PCI Express Graphics lane reversal input strap. Pull low on the carrier board to reverse

lane order. Be aware that the SDVO lines that share this interface do not necessarily

reverse order if this strap is low.

I 1.05V PEG_LANE_RV# is a boot strap signal

(see caution statement below)

SDVO_I2C_DAT

(SDVO_DATA)

C73 SDVO I²C data line to set up SDVO peripherals. I/O

OD 2.5V

SDVO_I2C_DAT is a boot strap signal

(see caution statement below)

Caution

The signals listed in the table above are used as chipset conguration straps during system reset. In this condition (during reset), they are

inputs that are pulled to the correct state by either COM Express™ internally implemented resistors or chipset internally implemented resistors

that are located on the module. No external DC loads or external pull-up or pull-down resistors should change the conguration of the signals

listed in the above table with the exception of PEG_LANE_RV# and SDVO_I2C_DAT. External resistors may override the internal strap states

and cause the COM Express™ module to malfunction and/or cause irreparable damage to the module.

SDVO_I2C_DAT can be pulled-up (using 5.6KΩ resistor) to 2.5V in order to set up SDVO peripherals.

PEG_LANE_RV# (only available on conga-B915 modules equipped with the Intel® 82915GME chipset) can be pulled low to activate lane

reversal mode.