User`s guide

Copyright © 2008 congatec AG B915m10 47/92
C-D Connector Signal Descriptions7.3
Table 18 PCI Signal Descriptions
Signal Pin # Description I/O PU/PD Comment
PCI_AD[0, 2, 4,
6, 8, 10, 12]
PCI_AD[1, 3,
5, 7]
PCI_AD[9, 11,
13, 15]
PCI_AD14
PCI_AD[16, 18,
20, 22]
PCI_AD[17, 19]
PCI_AD[21, 23]
PCI_AD[24, 26,
28, 30]
PCI_AD[25, 27,
29, 31]
C24-
C30
D22-
D25
D27-
D30
C32
D37-
D40
C39-C40
C42-C43
D42-
D45
C45-
C48
PCI bus multiplexed address and data lines I/O 3.3V
PCI_C/BE0#
PCI_C/BE1#
PCI_C/BE2#
PCI_C/BE3#
D26
C33
C38
C44
PCI bus byte enable lines, active low I/O 3.3V
PCI_DEVSEL# C36 PCI bus Device Select, active low. I/O 3.3V PU 8k2 3.3V
PCI_FRAME# D36 PCI bus Frame control line, active low. I/O 3.3V PU 8k2 3.3V
PCI_IRDY# C37 PCI bus Initiator Ready control line, active low. I/O 3.3V PU 8k2 3.3V
PCI_TRDY# D35 PCI bus Target Ready control line, active low. I/O 3.3V PU 8k2 3.3V
PCI_STOP# D34 PCI bus STOP control line, active low, driven by cycle initiator. I/O 3.3V PU 8k2 3.3V
PCI_PAR D32 PCI bus parity I/O 3.3V
PCI_PERR# C34 Parity Error: An external PCI device drives PERR# when it receives data that has a parity error. I/O 3.3V PU 8k2 3.3V
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
C22
C19
C17
D20
PCI bus master request input lines, active low. I 3.3V PU 8k2 3.3V
PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#
C20
C18
C16
D19
PCI bus master grant output lines, active low. O 3.3V
PCI_RESET# C23 PCI Reset output, active low. O 3.3V
PCI_LOCK# C35 PCI Lock control line, active low. I/O 3.3V PU 8k2 3.3V
PCI_SERR# D33 System Error: SERR# may be pulsed active by any PCI device that detects a system error condition. I/O 3.3V PU 8k2 3.3V
PCI_PME# C15 PCI Power Management Event: PCI peripherals drive PME# to wake system from low-power states S1–S5. I 3.3VSB
PCI_CLKRUN# D48 Bidirectional pin used to support PCI clock run protocol for mobile systems. I/O 3.3V PU 8k2 3.3V