User`s guide

A-B Connector Signal Descriptions7.1

Table 3 AC’97/Intel

High Denition Audio Link Signals Descriptions

Signal Pin # Description I/O PU/PD Comment

AC_RST# A30 AC ’97/Intel

High Denition Audio Reset: This signal is the master hardware reset to

external codec(s).

O 3.3V

AC_SYNC A29 AC ’97/Intel

High Denition Audio Sync: This signal is a 48 kHz xed rate sample

sync to the codec(s). It is also used to encode the stream number.

O 3.3V AC_SYNC is a boot strap signal (see note

below)

AC_BITCLK A32 AC ’97 Bit Clock Input: This signal is a 12.288 MHz serial data clock generated by the

external codec(s). This signal has an Intel

integrated pull-down resistor.

Intel

High Denition Audio Bit Clock Output: This signal is a 24.000MHz serial data

clock generated by the Intel

High Denition Audio controller (the Intel

ICH6). This

signal has an Intel

integrated pull-down resistor so that AC_BIT_CLK doesn’t oat when

an Intel

High Denition Audio codec (or no codec) is connected but the signals are

temporarily congured as AC ’97.

I 3.3V

O 3.3V

AC_SDOUT A33 AC ’97/Intel

High Denition Audio Serial Data Out: This signal is the serial TDM data

output to the codec(s). This serial output is double-pumped for a bit rate of 48 Mb/s for

Intel

High Denition Audio.

O 3.3V AC_SDOUT is a boot strap signal (see

note below)

AC_SDIN[2:0] B28-

B30

AC ’97//Intel

High Denition Audio Serial Data In [0]: These signals are serial TDM

data inputs from the three codecs. The serial input is single-pumped for a bit rate of 24

Mb/s for Intel

High Denition Audio.

I 3.3V

Note

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module.

For more information refer to section 7.5 of this user’s guide.